1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters

Takeshi UENO; Tomohiko ITO; Daisuke KUROSE; Takafumi YAMAJI; Tetsuro ITAKURA

doi:10.1093/ietfec/e91-a.2.454

1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters

Takeshi UENO, Tomohiko ITO, Daisuke KUROSE, Takafumi YAMAJI, Tetsuro ITAKURA

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This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.2 pp.454-460

Publication Date: 2008/02/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e91-a.2.454

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)

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Takeshi UENO, Tomohiko ITO, Daisuke KUROSE, Takafumi YAMAJI, Tetsuro ITAKURA, "1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters" in IEICE TRANSACTIONS on Fundamentals, vol. E91-A, no. 2, pp. 454-460, February 2008, doi: 10.1093/ietfec/e91-a.2.454.
Abstract: This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.2.454/_p

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@ARTICLE{e91-a_2_454,
author={Takeshi UENO, Tomohiko ITO, Daisuke KUROSE, Takafumi YAMAJI, Tetsuro ITAKURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters},
year={2008},
volume={E91-A},
number={2},
pages={454-460},
abstract={This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively.},
keywords={},
doi={10.1093/ietfec/e91-a.2.454},
ISSN={1745-1337},
month={February},}

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TY - JOUR
TI - 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 454
EP - 460
AU - Takeshi UENO
AU - Tomohiko ITO
AU - Daisuke KUROSE
AU - Takafumi YAMAJI
AU - Tetsuro ITAKURA
PY - 2008
DO - 10.1093/ietfec/e91-a.2.454
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2008
AB - This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively.
ER -