In this paper we propose a co-design method for control systems using combination of models. By co-design," we mean a cooperative design method in which the behavior of the entire system is simulated as a single model while parameters of the system are being optimized. Our co-design method enables the various subsystems in the system, which have been designed independently as tasks assigned to different designers in the traditional design method, to be designed simultaneously in a unified cooperative way from the system-wide perspective of a system designer. Our proposed method combines models of controlling and controlled subsystems into a single model for the behavior of the entire control system. After the optimum control conditions are determined through simulation of the combined models, based on the corresponding algorithms and parameters, ASIC design proceeds quickly with accurate verification using iterative replacements of the behavior model by the electronic circuit model. To evaluate the proposed method, we implemented a design environment. We then applied our method to the design of ASICs in three test cases (in a control system and in audio-visual systems) to investigate its effectiveness. This paper introduces the concepts of the proposed co-design method, the design environment and the experimental results, and points out the new issues for system design.

This paper proposes a top-down co-verification approach in the design of embedded systems composed of both hardware and software, for multimedia applications. In order to realize the optimized embedded system in cost, performance, power consumption and flexibility, hardware/software co-design becomes to be essential. In this top-down co-design flow, a target design is verified at three different levels: (1) algorithmic, (2) implementation, and (3) experimental. We have developed a methodology of top-down co-verification, which consists of the system level simulation at the algorithmic level, two type of co-simulations at the implementation level and the co-emulation at the experimental level. We have realized an environment optimized for verification performance by employing verification models appropriate to each verification stage and an efficient top-down environment by introducing the component logical bus architecture as the interface between hardware and software. Through actual application to a image compression and expansion system, the possibility of efficient co-verification was demonstrated.

Mobile communication services have become popular due to the rapid popularization of cellular mobile telephones. In order to offer services to an increasing number of users and to upgrade services, the development of Third-Generation Mobile Telecommunication is required. Our proposed system utilizing W-CDMA enables high-speed variable data communications, uninterrupted hand-over between communication zones, doubling of subscriber capacity and reduction of operation costs. Various actions are being taken internationally toward the establishment of a global standard for the Third-Generation Mobile Telecommunication System, aiming at its practical application around AD 2000. The W-CDMA system has been adopted as the standard for Japan. We are developing experimental W-CDMA system equipment. For this development, many Field Programmable Gate Array (FPGA) devices and Digital Signal Processors (DSP) have been used to meet the changes of equipment specifications and system evaluation parameters. By developing customized Large-scale Integrated circuit (LSI) devices and high-speed DSP, a small-size portable phone and a compact visual phone have been realized. Also, high-density mounting of the signal processing parts has been done in the Base Transceiver Station (BTS). In the development of a Mobile Communication Controller Simulator (MCC-SIM), the developmental period has been shortened by using our ATM switching system (AD8700) and generic-use PBX (Pana EXA) in the proposed system. In this paper, the features of the W-CDMA system and the outline of the newly developed experimental equipment have been described.

We propose a top-down approach for cosimulation of hardware/software co-designs for embedded systems and introduce a component logical bus architecture as an interface between software components implemented by processors and hardware components implemented by custom logic circuits. Co-simulation using a component logical bus architecture is possible is the same environment from the stage at which the processor is not yet finalized to the stage at which the processor is modeled in register transfer language. Models based upon a component logical bus architecture can be circulated and reused. We further describe experimental results of our approach.