A Method for Design of Embedded Systems for Multimedia Applications

Katsuhiko SEO; Hisao KOIZUMI; Barry SHACKLEFORD; Masashi MORI; Takashi KUSUHARA; Hirotaka KIMURA; Fumio SUZUKI

A Method for Design of Embedded Systems for Multimedia Applications

Katsuhiko SEO, Hisao KOIZUMI, Barry SHACKLEFORD, Masashi MORI, Takashi KUSUHARA, Hirotaka KIMURA, Fumio SUZUKI

Full Text Views

0

Share
Cite this

Summary :

This paper proposes a top-down co-verification approach in the design of embedded systems composed of both hardware and software, for multimedia applications. In order to realize the optimized embedded system in cost, performance, power consumption and flexibility, hardware/software co-design becomes to be essential. In this top-down co-design flow, a target design is verified at three different levels: (1) algorithmic, (2) implementation, and (3) experimental. We have developed a methodology of top-down co-verification, which consists of the system level simulation at the algorithmic level, two type of co-simulations at the implementation level and the co-emulation at the experimental level. We have realized an environment optimized for verification performance by employing verification models appropriate to each verification stage and an efficient top-down environment by introducing the component logical bus architecture as the interface between hardware and software. Through actual application to a image compression and expansion system, the possibility of efficient co-verification was demonstrated.

Publication: IEICE TRANSACTIONS on Electronics Vol.E81-C No.5 pp.725-732

Publication Date: 1998/05/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)

Category

Cite this

Copy

Katsuhiko SEO, Hisao KOIZUMI, Barry SHACKLEFORD, Masashi MORI, Takashi KUSUHARA, Hirotaka KIMURA, Fumio SUZUKI, "A Method for Design of Embedded Systems for Multimedia Applications" in IEICE TRANSACTIONS on Electronics, vol. E81-C, no. 5, pp. 725-732, May 1998, doi: .
Abstract: This paper proposes a top-down co-verification approach in the design of embedded systems composed of both hardware and software, for multimedia applications. In order to realize the optimized embedded system in cost, performance, power consumption and flexibility, hardware/software co-design becomes to be essential. In this top-down co-design flow, a target design is verified at three different levels: (1) algorithmic, (2) implementation, and (3) experimental. We have developed a methodology of top-down co-verification, which consists of the system level simulation at the algorithmic level, two type of co-simulations at the implementation level and the co-emulation at the experimental level. We have realized an environment optimized for verification performance by employing verification models appropriate to each verification stage and an efficient top-down environment by introducing the component logical bus architecture as the interface between hardware and software. Through actual application to a image compression and expansion system, the possibility of efficient co-verification was demonstrated.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e81-c_5_725/_p

Copy

@ARTICLE{e81-c_5_725,
author={Katsuhiko SEO, Hisao KOIZUMI, Barry SHACKLEFORD, Masashi MORI, Takashi KUSUHARA, Hirotaka KIMURA, Fumio SUZUKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Method for Design of Embedded Systems for Multimedia Applications},
year={1998},
volume={E81-C},
number={5},
pages={725-732},
abstract={This paper proposes a top-down co-verification approach in the design of embedded systems composed of both hardware and software, for multimedia applications. In order to realize the optimized embedded system in cost, performance, power consumption and flexibility, hardware/software co-design becomes to be essential. In this top-down co-design flow, a target design is verified at three different levels: (1) algorithmic, (2) implementation, and (3) experimental. We have developed a methodology of top-down co-verification, which consists of the system level simulation at the algorithmic level, two type of co-simulations at the implementation level and the co-emulation at the experimental level. We have realized an environment optimized for verification performance by employing verification models appropriate to each verification stage and an efficient top-down environment by introducing the component logical bus architecture as the interface between hardware and software. Through actual application to a image compression and expansion system, the possibility of efficient co-verification was demonstrated.},
keywords={},
doi={},
ISSN={},
month={May},}

Copy

TY - JOUR
TI - A Method for Design of Embedded Systems for Multimedia Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 725
EP - 732
AU - Katsuhiko SEO
AU - Hisao KOIZUMI
AU - Barry SHACKLEFORD
AU - Masashi MORI
AU - Takashi KUSUHARA
AU - Hirotaka KIMURA
AU - Fumio SUZUKI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1998
AB - This paper proposes a top-down co-verification approach in the design of embedded systems composed of both hardware and software, for multimedia applications. In order to realize the optimized embedded system in cost, performance, power consumption and flexibility, hardware/software co-design becomes to be essential. In this top-down co-design flow, a target design is verified at three different levels: (1) algorithmic, (2) implementation, and (3) experimental. We have developed a methodology of top-down co-verification, which consists of the system level simulation at the algorithmic level, two type of co-simulations at the implementation level and the co-emulation at the experimental level. We have realized an environment optimized for verification performance by employing verification models appropriate to each verification stage and an efficient top-down environment by introducing the component logical bus architecture as the interface between hardware and software. Through actual application to a image compression and expansion system, the possibility of efficient co-verification was demonstrated.
ER -