This paper presents the implementation of a 3 V low power multi-rate of 156, 622, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver using new parallel clock recovery architecture based on dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one-eighth frequency of the input data signal. Morevover, since the circuit works at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this recovery circuit can work with power dissipation of less than 40 mW with a single 3 V supply. All the simulations are based on HYUNDAI 0.65 µm N-Well CMOS double-poly double-metal technology.

The delta-sigma modulator (DSM) is an excellent choice for high-resolution analog-to-digital converters. Recently, a band-pass DSM has been a desirable choice for direct conversion of an IF signal into a digital bit stream. This paper proposes a quadrature band-pass DSM for digitizing a narrow-band IF signal. This modulator can achieve a lower total order, higher signal-to-noise ratio (SNR), and higher bandwidth when compared with conventional band-pass modulators. An experimental prototype employing the quadrature topology has been integrated in 0.6 µm, double-poly, double-metal CMOS technology with capacitors synthesized from a stacked poly structure. This system clocked at 13 MHz and digitized a 200 kHz bandwidth signal centered at 4.875 MHz with 100 dB of dynamic range. Power consumption is 190 mW at 5 V.

A single-chip ubiquitous sensor network (USN) system-on-a-chip (SoC) for small program memory size and low power has been proposed and integrated in a 0.18-µm CMOS technology. Proposed single-chip USN SoC is mainly consists of radio for 868/915 MHz, analog building block, complete digital baseband physical layer (PHY) and media access control (MAC) functions. The transceiver's analog building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, digital building block consists of differential binary phase-shift keying (DPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, embedded 8-bit microcontroller, and digital MAC function. Digital MAC function supports 128 bit advanced encryption standard (AES), cyclic redundancy check (CRC), inter-symbol timing check, MAC frame control, and automatic retransmission. These digital MAC functions reduce the processing power requirements of embedded microcontroller and program memory size by up to 56%. The cascaded noise figure and sensitivity of the overall receiver are 9.5 dB and -99 dBm, respectively. The overall transmitter achieves less than 6.3% error vector magnitude (EVM). The current consumption is 14 mA for reception mode and 16 mA for transmission mode.