A single-chip ubiquitous sensor network (USN) system-on-a-chip (SoC) for small program memory size and low power has been proposed and integrated in a 0.18-µm CMOS technology. Proposed single-chip USN SoC is mainly consists of radio for 868/915 MHz, analog building block, complete digital baseband physical layer (PHY) and media access control (MAC) functions. The transceiver's analog building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, digital building block consists of differential binary phase-shift keying (DPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, embedded 8-bit microcontroller, and digital MAC function. Digital MAC function supports 128 bit advanced encryption standard (AES), cyclic redundancy check (CRC), inter-symbol timing check, MAC frame control, and automatic retransmission. These digital MAC functions reduce the processing power requirements of embedded microcontroller and program memory size by up to 56%. The cascaded noise figure and sensitivity of the overall receiver are 9.5 dB and -99 dBm, respectively. The overall transmitter achieves less than 6.3% error vector magnitude (EVM). The current consumption is 14 mA for reception mode and 16 mA for transmission mode.
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Dong-Sun KIM, Hae-Moon SEO, Seung-Yerl LEE, Yeon-Kug MOON, Byung-Soo KIM, Tae-Ho HWANG, Duck-Jin CHUNG, "A Fully Integrated SoC with Digital MAC Processor and Transceiver for Ubiquitous Sensor Network at 868/915 MHz" in IEICE TRANSACTIONS on Communications,
vol. E90-B, no. 12, pp. 3336-3345, December 2007, doi: 10.1093/ietcom/e90-b.12.3336.
Abstract: A single-chip ubiquitous sensor network (USN) system-on-a-chip (SoC) for small program memory size and low power has been proposed and integrated in a 0.18-µm CMOS technology. Proposed single-chip USN SoC is mainly consists of radio for 868/915 MHz, analog building block, complete digital baseband physical layer (PHY) and media access control (MAC) functions. The transceiver's analog building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, digital building block consists of differential binary phase-shift keying (DPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, embedded 8-bit microcontroller, and digital MAC function. Digital MAC function supports 128 bit advanced encryption standard (AES), cyclic redundancy check (CRC), inter-symbol timing check, MAC frame control, and automatic retransmission. These digital MAC functions reduce the processing power requirements of embedded microcontroller and program memory size by up to 56%. The cascaded noise figure and sensitivity of the overall receiver are 9.5 dB and -99 dBm, respectively. The overall transmitter achieves less than 6.3% error vector magnitude (EVM). The current consumption is 14 mA for reception mode and 16 mA for transmission mode.
URL: https://globals.ieice.org/en_transactions/communications/10.1093/ietcom/e90-b.12.3336/_p
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@ARTICLE{e90-b_12_3336,
author={Dong-Sun KIM, Hae-Moon SEO, Seung-Yerl LEE, Yeon-Kug MOON, Byung-Soo KIM, Tae-Ho HWANG, Duck-Jin CHUNG, },
journal={IEICE TRANSACTIONS on Communications},
title={A Fully Integrated SoC with Digital MAC Processor and Transceiver for Ubiquitous Sensor Network at 868/915 MHz},
year={2007},
volume={E90-B},
number={12},
pages={3336-3345},
abstract={A single-chip ubiquitous sensor network (USN) system-on-a-chip (SoC) for small program memory size and low power has been proposed and integrated in a 0.18-µm CMOS technology. Proposed single-chip USN SoC is mainly consists of radio for 868/915 MHz, analog building block, complete digital baseband physical layer (PHY) and media access control (MAC) functions. The transceiver's analog building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, digital building block consists of differential binary phase-shift keying (DPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, embedded 8-bit microcontroller, and digital MAC function. Digital MAC function supports 128 bit advanced encryption standard (AES), cyclic redundancy check (CRC), inter-symbol timing check, MAC frame control, and automatic retransmission. These digital MAC functions reduce the processing power requirements of embedded microcontroller and program memory size by up to 56%. The cascaded noise figure and sensitivity of the overall receiver are 9.5 dB and -99 dBm, respectively. The overall transmitter achieves less than 6.3% error vector magnitude (EVM). The current consumption is 14 mA for reception mode and 16 mA for transmission mode.},
keywords={},
doi={10.1093/ietcom/e90-b.12.3336},
ISSN={1745-1345},
month={December},}
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TY - JOUR
TI - A Fully Integrated SoC with Digital MAC Processor and Transceiver for Ubiquitous Sensor Network at 868/915 MHz
T2 - IEICE TRANSACTIONS on Communications
SP - 3336
EP - 3345
AU - Dong-Sun KIM
AU - Hae-Moon SEO
AU - Seung-Yerl LEE
AU - Yeon-Kug MOON
AU - Byung-Soo KIM
AU - Tae-Ho HWANG
AU - Duck-Jin CHUNG
PY - 2007
DO - 10.1093/ietcom/e90-b.12.3336
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E90-B
IS - 12
JA - IEICE TRANSACTIONS on Communications
Y1 - December 2007
AB - A single-chip ubiquitous sensor network (USN) system-on-a-chip (SoC) for small program memory size and low power has been proposed and integrated in a 0.18-µm CMOS technology. Proposed single-chip USN SoC is mainly consists of radio for 868/915 MHz, analog building block, complete digital baseband physical layer (PHY) and media access control (MAC) functions. The transceiver's analog building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, digital building block consists of differential binary phase-shift keying (DPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, embedded 8-bit microcontroller, and digital MAC function. Digital MAC function supports 128 bit advanced encryption standard (AES), cyclic redundancy check (CRC), inter-symbol timing check, MAC frame control, and automatic retransmission. These digital MAC functions reduce the processing power requirements of embedded microcontroller and program memory size by up to 56%. The cascaded noise figure and sensitivity of the overall receiver are 9.5 dB and -99 dBm, respectively. The overall transmitter achieves less than 6.3% error vector magnitude (EVM). The current consumption is 14 mA for reception mode and 16 mA for transmission mode.
ER -