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[Author] Seung-Yerl LEE(2hit)

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  • Dual Priority Scheduling Based on Power Adjustment Context Switching for Ubiquitous Sensor Network

    Dong-Sun KIM  Taeo HWANG  Seung-Yerl LEE  Kwang-Ho WON  Byung-Soo KIM  Seong-Dong KIM  Duck-Jin CHUNG  

     
    PAPER

      Vol:
    E90-B No:12
      Page(s):
    3419-3425

    The Ubiquitous sensor network (USN) node is required to operate for several months with limited system resources such as memory and power. The typical USN node is in the active state for less than 1% of its several month lifetime and waits in the inactive state for the remaining 99% of its lifetime. This paper suggests a power adjustment dual priority scheduler (PA-DPS) that offers low power consumption while meeting the USN requirements by estimating power consumption in the USN node. PA-DPS has been designed based on the event-driven approach and the dual-priority scheduling structure, which has been conventionally suggested in the real-time system field. From experimental results, PA-DPS reduced the inactive mode current up to 40% under the 1% duty cycle.

  • A Fully Integrated SoC with Digital MAC Processor and Transceiver for Ubiquitous Sensor Network at 868/915 MHz

    Dong-Sun KIM  Hae-Moon SEO  Seung-Yerl LEE  Yeon-Kug MOON  Byung-Soo KIM  Tae-Ho HWANG  Duck-Jin CHUNG  

     
    PAPER

      Vol:
    E90-B No:12
      Page(s):
    3336-3345

    A single-chip ubiquitous sensor network (USN) system-on-a-chip (SoC) for small program memory size and low power has been proposed and integrated in a 0.18-µm CMOS technology. Proposed single-chip USN SoC is mainly consists of radio for 868/915 MHz, analog building block, complete digital baseband physical layer (PHY) and media access control (MAC) functions. The transceiver's analog building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, digital building block consists of differential binary phase-shift keying (DPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, embedded 8-bit microcontroller, and digital MAC function. Digital MAC function supports 128 bit advanced encryption standard (AES), cyclic redundancy check (CRC), inter-symbol timing check, MAC frame control, and automatic retransmission. These digital MAC functions reduce the processing power requirements of embedded microcontroller and program memory size by up to 56%. The cascaded noise figure and sensitivity of the overall receiver are 9.5 dB and -99 dBm, respectively. The overall transmitter achieves less than 6.3% error vector magnitude (EVM). The current consumption is 14 mA for reception mode and 16 mA for transmission mode.

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