An analytical method to make a trade off between tuning range and differential non-linearity (DNL) for a digitally controlled oscillator (DCO) is proposed. To verify the approach, a 12 bit DCO is designed, implemented in 0.18 µm CMOS technology, and tested. The measured DNL was -0.41 Least Significant Bit (LSB) without degrading other parameters which is the best so far among the reported DCOs.

High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18µm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270×280µm2. The full-chip post layout simulation results show 2.54GHz oscillation frequency, 2.2mA current consumption and phase noise of -123dBc/Hz at 1MHz offset.

This Letter employs transmission-line theory for the impedance-matching circuits for a single-chip power amplifier (PA) and verifies for 5 GHz-band wireless LAN (IEEE 802.11a) applications. The presented matching circuits are composed of conductor-backed coplanar waveguide (CPW) meander-line resonators and impedance (K) inverters. One of the advantages of the presented circuits is that it can save on-chip space occupied by the matching circuits compared to that using the spiral inductors, thus reducing the cost. The prototype chip, which consists of PA and matching circuits, is designed employing the presented theory and fabricated. A few of the measured results to verify the design theory are presented.

We propose the new and highly accurate design theory of the high Tc superconducting (HTS) miniaturized coplanar waveguide (CPW) bandpass filters (BPFs) with highly packed meanderlines. BPFs are designed using the external quality factor (Qe) and coupling constant (k) (Q-k method). These parameters are estimated from the transmission coefficient obtained by the 2.5-dimensional electromagnetic field simulator. Moreover, the Q-k method is compared with the J-b method (designed using admittance inverter and susceptance slope parameter) presented previously; in this way we confirmed that the Q-k method has higher accuracy than the J-b method. We realized the design of a the highly packed meanderline CPW BPF (5 pole, center frequency = 2 GHz, fractional band width = 15 MHz, ripple = 0.1 dB) in a 3.5 mm 8 mm substrate.

A method to realize the fine frequency-tuning steps using tiny capacitors instead of Metal-Insulator-Metal (MIM) capacitors is proposed for a digitally controlled oscillator (DCO). The tiny capacitors are realized by the coplanar transmission lines which are arranged unsymmetrical in a 6 metal layers (M6) foundry of 0.18 µm CMOS technology. These transmission line based capacitors are designed by using electro-magnetic field simulator, and co-designed by using SPICE simulator. Finally, these capacitors are employed to design 15 bit DCO and fabricated the proposed DCO in 0.18 µm CMOS technology, and tested. The measured phase noise of DCO was -118.3 dBc/Hz (@1 MHz offset frequency), and the oscillating frequency tuned from 4.86 GHz to 5.36 GHz in the minimum frequency-tuning step of 18 kHz.

As an RF high Tc superconducting (HTS) front end for a microwave receiver, we propose a new design method for the broadband matching circuit composed of coplanar waveguide (CPW) meanderline resonators connecting a slot antenna with CMOS low noise amplifier (LNA). The parameters of the antenna sections with matching circuit are calculated and simulated with the circuit simulator and electromagnetic field simulator. CMOS LNA was designed and its input and output impedances and noise figure were obtained by SPICE simulation.

This paper looks into the underlying RF energy harvesting issues at low input ambient power levels below 0 dBm where efficiency degradation is severe. The proposed design aims to improve the rectenna sensitivity, efficiency, and output DC power. In the same manner, we are using a straightforward and compact size rectenna design. The receiving antenna is a coplanar waveguide (CPW) slot monopole antenna with harmonic suppression property and a peak measured gain of 3 dBi. Also, an improved antenna radiation characteristics, e.g radiation pattern and gain covering the desired operating band (ISM 2.45 GHz), is observed. The rectifier is a voltage doubler circuit based on microstrip (MS) structure. Two architectures of rectenna were carefully designed, fabricated and tested. The first layout; antenna, and rectifier were fabricated separately and then connected using a connector. The peak efficiency (40% at -5 dBm) achieved is lower than expected. To improve the efficiency, a high compactness and simple integration between antenna and rectifier are achieved by using a smooth CPW-MS transition. This design shows improved conversion efficiency measurement results which typically agree with the simulation results. The measured peak conversion efficiency is 72% at RF power level of -7 dBm and a load resistance of 2 kΩ.

This paper presents the design and implementation of a quadrature voltage-controlled ring oscillator with the improved figure of merit (FOM) using the four single-ended inverter topology. Furthermore, a new architecture to prevent the latch-up in even number of stages composed of single-ended ring inverters is proposed. The design is implemented in 0.18 µm CMOS technology and the measurement results show a FOM of -163.8 dBc/Hz with the phase noise of -125.8 dBc/Hz at 4 MHz offset from the carrier frequency of 3.4 GHz. It exhibits a frequency tuning range from 1.23 GHz to 4.17 GHz with coarse and fine frequency tuning sensitivity of 1.08 MHz/mV and 120 kHz/mV, respectively.

In order to reduce the size of a wireless system, we propose a design theory for the broadband impedance matching circuit which connects an electrically small antenna (ESA) to a semiconductor amplifier. We confirmed its validity for the case of connection between a small slot loop antenna with a small radiation resistance of Ra =0.776 Ω and a semiconductor amplifier with high input impedance of ZL =321-j871 Ω with the aid of the simulations by the electrical circuits using transmission lines as well as the electromagnetic field (EM field) simulator. We also made experiments on this antenna with matching circuits using high temperature superconductor YBCO thin films on MgO substrates.

High phase noise is a common problem in ring oscillators. Continuous conduction of the transistor in an analog tuning method degrades the phase noise of ring oscillators. In this paper, a digital control tuning which completely switches the transistors on and off, and a 1/f noise reduction technique are employed to reduce the phase noise. A 14-bit control signal is employed to obtain a small frequency step and a wide tuning range. Furthermore, multiphase ring oscillator with a sub-feedback loop topology is used to obtain a stable quadrature outputs with even number of stages and to increase the output frequency. The measured DCO has a frequency tuning range from 554 MHz to 2.405 GHz. The power dissipation is 112 mW from 1.8 V power supply. The phase noise at 4 MHz offset and 2.4 GHz center frequency is -134.82 dBc/Hz. The FoM is -169.9 dBc/Hz which is a 6.3 dB improvement over the previous oscillator design.

We propose a design theory of the miniaturized high temperature superconducting (HTS) coplanar waveguide (CPW) bandpass filter (BPF), which is composed of meanderline quarter-wavelength resonator, J- and K-inverters. The J- and K-inverters are realized by using interdigital gap and meander-shape inductor. To evaluate the kinetic inductance of the K-inverter, we fabricate the YBCO resonator connected with K-inverters and redesigned the YBCO filter parameters. Finally, we designed and fabricated the YBCO CPW quarter-wavelength resonator BPF by taking account of the kinetic inductance of the K-inverter. The experimental results are in agreement with the design parameters.

Recently, spiral inductors have widely been used instead of resistors in the design of matching circuits to enhance the thermal noise performance of a wireless transceiver. However, such elements usually have low quality factor (Q) and may encounter the self-resonance in microwave-frequency band which permits its use in higher frequencies, and on the other hand, they occupy the large on-chip space. This paper presents a new design theory for the impedance-matching circuits for a single-chip SiGe BiCMOS receiver front-end for 2.4 GHz-band wireless LAN (IEEE 802.11b). The presented matching circuits are composed of conductor-backed coplanar waveguide (CPW) meander-line resonators and impedance (K) inverter. The prototype front-end receiver is designed, fabricated and tested. A few of the measured results to verify the design theory are presented.

This paper presents the design and implementation of 0.9–4.8 GHz CMOS power amplifier (PA) with improved group delay variation and gain flatness at the same time for UWB transmitters. This PA design employs a two-stage cascade common source topology, a resistive shunt feedback technique and inductive peaking to achieve high gain flatness, and good input matching. Based on theoretical analysis, the main design factor for group delay variation is identified. The measurement results indicate that the proposed PA design has an average gain of 10.2 ± 0.8 dB while maintaining a 3-dB bandwidth of 0.57 to 5.8 GHz, an input return loss |S11| less than -4.4 dB, and an output return loss |S22| less than -9.2 dB over the frequency range of interest. The input 1 dB compression point at 2 GHz was -9 dBm while consumes 30 mW power from 1.5 V supply voltage. Moreover, excellent phase linearity (i.e., group delay variation) of ±125 ps was achieved across the whole band.

This paper presents the design of a second-order and a fourth-order bandpass filter (BPF) for 60 GHz millimeter-wave applications in 0.18 µm CMOS technology. The proposed on-chip BPFs employ the folded open loop structure designed on pattern ground shields. The adoption of a folded structure and utilization of multiple transmission zeros in the stopband permit the compact size and high selectivity for the BPF. Moreover, the pattern ground shields obviously slow down the guided waves which enable further reduction in the physical length of the resonator, and this, in turn, results in improvement of the insertion losses. A very good agreement between the electromagnetic (EM) simulations and measurement results has been achieved. As a result, the second-order BPF has the center frequency of 57.5 GHz, insertion loss of 2.77 dB, bandwidth of 14 GHz, return loss less than 27.5 dB and chip size of 650 µm810 µm (including bonding pads) while the fourth-order BPF has the center frequency of 57 GHz, insertion loss of 3.06 dB, bandwidth of 12 GHz, return loss less than 30 dB with chip size of 905 µm810 µm (including bonding pads).

2-pole band-pass filters (BPFs) with tap-excitation are prepared by using high temperature superconductors (HTS). The possibility of realizing superconducting coplanar filters with attenuation poles is revealed.

The analysis and design of a full 360 degrees hybrid coupler phase shifter with integrated distributed elements low pass filters is presented. Pi-section filter is incorporated into hybrid coupler phase shifter for harmonic suppression. The physical size of the proposed structure is close to that of the conventional hybrid coupler phase shifter. The maximum phase shift range is bounded by the port impedance ratio of the hybrid coupler phase shifter. Furthermore, the phase shift range is reduced if series inductance in the reflective load deviates from the optimum value. Numerical and parametric analyses are used to find the equivalent circuit of the pi-section filter for consistent relative phase shift. To validate our analysis, the proposed phase shifter operates at 8.6GHz was fabricated and measured. Over the frequency range of interest, the fabricated phase shifter suppresses second harmonic and achieves analog phase shift of 0 to 360 degrees at the passband, agreeing with the theoretical and simulation results.