A Wide Range CMOS Power Amplifier with Improved Group Delay Variation and Gain Flatness for UWB Transmitters

Rohana SAPAWI; Ramesh K. POKHAREL; Haruichi KANAYA; Keiji YOSHIDA

doi:10.1587/transele.E95.C.1182

A Wide Range CMOS Power Amplifier with Improved Group Delay Variation and Gain Flatness for UWB Transmitters

Rohana SAPAWI, Ramesh K. POKHAREL, Haruichi KANAYA, Keiji YOSHIDA

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This paper presents the design and implementation of 0.9–4.8 GHz CMOS power amplifier (PA) with improved group delay variation and gain flatness at the same time for UWB transmitters. This PA design employs a two-stage cascade common source topology, a resistive shunt feedback technique and inductive peaking to achieve high gain flatness, and good input matching. Based on theoretical analysis, the main design factor for group delay variation is identified. The measurement results indicate that the proposed PA design has an average gain of 10.2 ± 0.8 dB while maintaining a 3-dB bandwidth of 0.57 to 5.8 GHz, an input return loss |S₁₁| less than -4.4 dB, and an output return loss |S₂₂| less than -9.2 dB over the frequency range of interest. The input 1 dB compression point at 2 GHz was -9 dBm while consumes 30 mW power from 1.5 V supply voltage. Moreover, excellent phase linearity (i.e., group delay variation) of ±125 ps was achieved across the whole band.

Publication: IEICE TRANSACTIONS on Electronics Vol.E95-C No.7 pp.1182-1188

Publication Date: 2012/07/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E95.C.1182

Type of Manuscript: Special Section PAPER (Special Section on Recent Trends of Microwave Systems and Their Fundamental Technologies)

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Rohana SAPAWI, Ramesh K. POKHAREL, Haruichi KANAYA, Keiji YOSHIDA, "A Wide Range CMOS Power Amplifier with Improved Group Delay Variation and Gain Flatness for UWB Transmitters" in IEICE TRANSACTIONS on Electronics, vol. E95-C, no. 7, pp. 1182-1188, July 2012, doi: 10.1587/transele.E95.C.1182.
Abstract: This paper presents the design and implementation of 0.9–4.8 GHz CMOS power amplifier (PA) with improved group delay variation and gain flatness at the same time for UWB transmitters. This PA design employs a two-stage cascade common source topology, a resistive shunt feedback technique and inductive peaking to achieve high gain flatness, and good input matching. Based on theoretical analysis, the main design factor for group delay variation is identified. The measurement results indicate that the proposed PA design has an average gain of 10.2 ± 0.8 dB while maintaining a 3-dB bandwidth of 0.57 to 5.8 GHz, an input return loss |S₁₁| less than -4.4 dB, and an output return loss |S₂₂| less than -9.2 dB over the frequency range of interest. The input 1 dB compression point at 2 GHz was -9 dBm while consumes 30 mW power from 1.5 V supply voltage. Moreover, excellent phase linearity (i.e., group delay variation) of ±125 ps was achieved across the whole band.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.1182/_p

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@ARTICLE{e95-c_7_1182,
author={Rohana SAPAWI, Ramesh K. POKHAREL, Haruichi KANAYA, Keiji YOSHIDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Wide Range CMOS Power Amplifier with Improved Group Delay Variation and Gain Flatness for UWB Transmitters},
year={2012},
volume={E95-C},
number={7},
pages={1182-1188},
abstract={This paper presents the design and implementation of 0.9–4.8 GHz CMOS power amplifier (PA) with improved group delay variation and gain flatness at the same time for UWB transmitters. This PA design employs a two-stage cascade common source topology, a resistive shunt feedback technique and inductive peaking to achieve high gain flatness, and good input matching. Based on theoretical analysis, the main design factor for group delay variation is identified. The measurement results indicate that the proposed PA design has an average gain of 10.2 ± 0.8 dB while maintaining a 3-dB bandwidth of 0.57 to 5.8 GHz, an input return loss |S₁₁| less than -4.4 dB, and an output return loss |S₂₂| less than -9.2 dB over the frequency range of interest. The input 1 dB compression point at 2 GHz was -9 dBm while consumes 30 mW power from 1.5 V supply voltage. Moreover, excellent phase linearity (i.e., group delay variation) of ±125 ps was achieved across the whole band.},
keywords={},
doi={10.1587/transele.E95.C.1182},
ISSN={1745-1353},
month={July},}

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TY - JOUR
TI - A Wide Range CMOS Power Amplifier with Improved Group Delay Variation and Gain Flatness for UWB Transmitters
T2 - IEICE TRANSACTIONS on Electronics
SP - 1182
EP - 1188
AU - Rohana SAPAWI
AU - Ramesh K. POKHAREL
AU - Haruichi KANAYA
AU - Keiji YOSHIDA
PY - 2012
DO - 10.1587/transele.E95.C.1182
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2012
AB - This paper presents the design and implementation of 0.9–4.8 GHz CMOS power amplifier (PA) with improved group delay variation and gain flatness at the same time for UWB transmitters. This PA design employs a two-stage cascade common source topology, a resistive shunt feedback technique and inductive peaking to achieve high gain flatness, and good input matching. Based on theoretical analysis, the main design factor for group delay variation is identified. The measurement results indicate that the proposed PA design has an average gain of 10.2 ± 0.8 dB while maintaining a 3-dB bandwidth of 0.57 to 5.8 GHz, an input return loss |S₁₁| less than -4.4 dB, and an output return loss |S₂₂| less than -9.2 dB over the frequency range of interest. The input 1 dB compression point at 2 GHz was -9 dBm while consumes 30 mW power from 1.5 V supply voltage. Moreover, excellent phase linearity (i.e., group delay variation) of ±125 ps was achieved across the whole band.
ER -