An analytical method to make a trade off between tuning range and differential non-linearity (DNL) for a digitally controlled oscillator (DCO) is proposed. To verify the approach, a 12 bit DCO is designed, implemented in 0.18 µm CMOS technology, and tested. The measured DNL was -0.41 Least Significant Bit (LSB) without degrading other parameters which is the best so far among the reported DCOs.

A 1.9GHz film bulk acoustic resonator (FBAR)-based low-phase-noise complementary cross-coupled voltage-controlled oscillator (VCO) is presented. The FBAR-VCO is designed and fabricated in 0.18µm CMOS process. The DC latch and the low frequency instability are resolved by employing the NMOS source coupling capacitor and the DC blocked cross-coupled pairs. Since no additional voltage headroom is required, the proposed FBAR-VCO can be operated at a low power supply voltage of 1.1V with a wide voltage swing of 0.9V. An effective phase noise optimization is realized by a reasonable trade-off between the output resistance and the trans-conductance of the cross-coupled pairs. The measured performance shows the proposed FBAR-VCO achieves a phase noise of -148dBc/Hz at 1MHz offset with a figure of merit (FoM) of -211.6dB.

Electromagnetic (EM) wave absorbers have been used for improving the EM environment of an electronic toll collection (ETC) system on an express highway or a wireless local area network (LAN) system in an indoor environment. In this paper, an efficient multi-ray propagation model, which uses 3D geometry and image techniques to trace multiple signal rays from transmitter to receiver, is employed to analyze the EM environment of a dedicated short-range communication (DSRC) system on an express highway. The validity of the model employed is discussed by the comparison with the results obtained by an experiment on the highways. The analysis shows that the possible undesired communications between onboard equipment that acts as a receiver and DSRC beacon which transmits the radio signals, is improved by increasing the EM wave-absorption capability of the sidewalls and the pavement of the highway. Another advantage of the employed model is that it is effective for investigating the location of wave absorbers to be set up on the highway, and it takes only a fraction of a minute for computation.

A method to realize the fine frequency-tuning steps using tiny capacitors instead of Metal-Insulator-Metal (MIM) capacitors is proposed for a digitally controlled oscillator (DCO). The tiny capacitors are realized by the coplanar transmission lines which are arranged unsymmetrical in a 6 metal layers (M6) foundry of 0.18 µm CMOS technology. These transmission line based capacitors are designed by using electro-magnetic field simulator, and co-designed by using SPICE simulator. Finally, these capacitors are employed to design 15 bit DCO and fabricated the proposed DCO in 0.18 µm CMOS technology, and tested. The measured phase noise of DCO was -118.3 dBc/Hz (@1 MHz offset frequency), and the oscillating frequency tuned from 4.86 GHz to 5.36 GHz in the minimum frequency-tuning step of 18 kHz.

In a partially coupled-line bandpass filter (BPF), a combination of two microstrip line resonators which are partially coupled, are considered, where one resonator is half-wavelength (λ/2)-long, and another whose one end is grounded, is only quarter-wavelength (λ/4)-long. Therefore, the length of a coupled-line section can be varied based on the position of the grounding end, and five conditions of the movable coupling length have been simulated which will greatly influence the spurious responses of a BPF. This property is numerically investigated in this paper. The analysis shows that, based on the grounding position, this method is capable of realizing the improved out-of-band characteristics by locating the multiple attenuation poles in the stopband and improved spurious responses up to five times of the center frequency (5f0). A few empirical models of BPF are fabricated, and the numerical results are ensured by comparing with the experimental results.

In this letter, we discuss the measurement error due to the exclusion of the higher modes when a waveguide with a flange is inserted with lossy dielectric material. The reflection coefficient is calculated by a spectrum-domain approach (SDA), which uses only the dominant (TE10) mode to realize a simplified nondestructive measurement of complex permittivity of lossy dielectric sheets. The analysis shows that the error due to the exclusion of the higher modes decreases as complex permittivity increases. Consequently, we have confirmed that a simplified measurement of complex permittivity is possible by a coverage limitation with the SDA, which excludes the higher modes.

This paper presents the design and implementation of a quadrature voltage-controlled ring oscillator with the improved figure of merit (FOM) using the four single-ended inverter topology. Furthermore, a new architecture to prevent the latch-up in even number of stages composed of single-ended ring inverters is proposed. The design is implemented in 0.18 µm CMOS technology and the measurement results show a FOM of -163.8 dBc/Hz with the phase noise of -125.8 dBc/Hz at 4 MHz offset from the carrier frequency of 3.4 GHz. It exhibits a frequency tuning range from 1.23 GHz to 4.17 GHz with coarse and fine frequency tuning sensitivity of 1.08 MHz/mV and 120 kHz/mV, respectively.

High phase noise is a common problem in ring oscillators. Continuous conduction of the transistor in an analog tuning method degrades the phase noise of ring oscillators. In this paper, a digital control tuning which completely switches the transistors on and off, and a 1/f noise reduction technique are employed to reduce the phase noise. A 14-bit control signal is employed to obtain a small frequency step and a wide tuning range. Furthermore, multiphase ring oscillator with a sub-feedback loop topology is used to obtain a stable quadrature outputs with even number of stages and to increase the output frequency. The measured DCO has a frequency tuning range from 554 MHz to 2.405 GHz. The power dissipation is 112 mW from 1.8 V power supply. The phase noise at 4 MHz offset and 2.4 GHz center frequency is -134.82 dBc/Hz. The FoM is -169.9 dBc/Hz which is a 6.3 dB improvement over the previous oscillator design.

Characteristics of a class of stepped-impedance resonators (SIRs) which is loaded with two dielectric rods, are investigated by a Finite-Difference Time-Domain (FDTD) method. Dielectric rods to be inserted between a strip conductor and the ground plane have higher relative permittivity than that of the substrate. When a tapped half-wavelength (λ/2) microstrip resonator is loaded with two dielectric rods, the electric length of a loaded λ/2 resonator becomes longer than λ/2, which makes its fundamental resonant frequency () to be generated on the region lower than that of an unloaded λ/2 resonator (fr) and its first spurious response (fsp1) is generated on the region higher than 2. Therefore, to shift back to fr, the resonator's length is to be reduced, and this, in turns, suppress the spurious responses. Then, the resonant characteristics of an SIR employing the proposed method has also been investigated, and it is found that this is capable of suppressing the spurious responses in wideband together with an attenuation pole in the stopband, and of further reducing the resonator's length. Therefore, wide exploitation of the presented method can be expected in the filter design based on the LTCC technique.

Recently, spiral inductors have widely been used instead of resistors in the design of matching circuits to enhance the thermal noise performance of a wireless transceiver. However, such elements usually have low quality factor (Q) and may encounter the self-resonance in microwave-frequency band which permits its use in higher frequencies, and on the other hand, they occupy the large on-chip space. This paper presents a new design theory for the impedance-matching circuits for a single-chip SiGe BiCMOS receiver front-end for 2.4 GHz-band wireless LAN (IEEE 802.11b). The presented matching circuits are composed of conductor-backed coplanar waveguide (CPW) meander-line resonators and impedance (K) inverter. The prototype front-end receiver is designed, fabricated and tested. A few of the measured results to verify the design theory are presented.

This paper presents the design and implementation of 0.9–4.8 GHz CMOS power amplifier (PA) with improved group delay variation and gain flatness at the same time for UWB transmitters. This PA design employs a two-stage cascade common source topology, a resistive shunt feedback technique and inductive peaking to achieve high gain flatness, and good input matching. Based on theoretical analysis, the main design factor for group delay variation is identified. The measurement results indicate that the proposed PA design has an average gain of 10.2 ± 0.8 dB while maintaining a 3-dB bandwidth of 0.57 to 5.8 GHz, an input return loss |S11| less than -4.4 dB, and an output return loss |S22| less than -9.2 dB over the frequency range of interest. The input 1 dB compression point at 2 GHz was -9 dBm while consumes 30 mW power from 1.5 V supply voltage. Moreover, excellent phase linearity (i.e., group delay variation) of ±125 ps was achieved across the whole band.

This paper presents the design of a second-order and a fourth-order bandpass filter (BPF) for 60 GHz millimeter-wave applications in 0.18 µm CMOS technology. The proposed on-chip BPFs employ the folded open loop structure designed on pattern ground shields. The adoption of a folded structure and utilization of multiple transmission zeros in the stopband permit the compact size and high selectivity for the BPF. Moreover, the pattern ground shields obviously slow down the guided waves which enable further reduction in the physical length of the resonator, and this, in turn, results in improvement of the insertion losses. A very good agreement between the electromagnetic (EM) simulations and measurement results has been achieved. As a result, the second-order BPF has the center frequency of 57.5 GHz, insertion loss of 2.77 dB, bandwidth of 14 GHz, return loss less than 27.5 dB and chip size of 650 µm810 µm (including bonding pads) while the fourth-order BPF has the center frequency of 57 GHz, insertion loss of 3.06 dB, bandwidth of 12 GHz, return loss less than 30 dB with chip size of 905 µm810 µm (including bonding pads).

This paper presents a new method to improve the resonant characteristics of a microstrip resonator. The improved characteristics have been achieved by inserting two dielectric rods between strip conductor and the ground plane. Dielectric rods to be inserted have higher relative permittivity than that of the substrate. Therefore, it is suitable to realize by Low-Temperature Cofired Ceramics (LTCC) technique. Several model of microstrip resonators employing the proposed method are analyzed by a Finite-Difference Time-Domain (FDTD) method, and their resonant characteristics are discussed. One of the advantages of the proposed method is that an attenuation pole (fl or fh) in each side of the fundamental resonant frequency (fr) and improved-spurious responses can be realized together by a capacitive-coupling tapped resonator loaded with dielectric rods. The proposed method is also effective to achieve sharp skirt characteristics and wide stopband of a direct-coupling tapped resonator which can be used either as a wideband lowpass filter or a band-elimination filter. Another interesting feature of the analyzed resonators is that about 60% reduction in resonator's length has been obtained compared to a basic half-wavelength (λ/2) microstrip resonator. Therefore, wide exploitation of the proposed method can be expected in the filter design based on the LTCC technique.