This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore, total memory requirements can be minimized.

This paper proposes a built-in self-test (BIST) scheme for noise-tolerant testing of a digital-to-analogue converter (DAC). The proposed BIST calculates the differences in output voltages between a DAC and test modules. These differences are used as the inputs of an integrator that determines integral nonlinearity (INL). The proposed method has an advantage of random noise cancelation and achieves a higher test accuracy than do the conventional BIST methods. The simulation results show high standard noise-immunity and fault coverage for the proposed method.

This paper proposes a new pattern matching architecture with multi-character processing for deep packet inspection. The proposed pattern matching architecture detects the start point of pattern matching from multi-character input using input text alignment. By eliminating duplicate hardware components using process element tree, hardware cost is greatly reduced in the proposed pattern matching architecture.

This paper proposes the minimum transition random X-filling (MTR-fill) technique, which is a new X-filling method, to reduce the amount of power dissipation during scan-based testing. In order to model the amount of power dissipated during scan load/unload cycles, the total weighted transition metric (TWTM) is introduced, which is calculated by the sum of the weighted transitions in a scan-load of a test pattern and a scan-unload of a test response. The proposed MTR-fill is implemented by simulated annealing method. During the annealing process, the TWTM of a pair of test patterns and test responses are minimized. Simultaneously, the MTR-fill attempts to increase the randomness of test patterns in order to reduce the number of test patterns needed to achieve adequate fault coverage. The effectiveness of the proposed technique is shown through experiments for ISCAS'89 benchmark circuits.