Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure including source/drain (S/D) profile was carried out for hp45 low standby power (LSTP) device whose gate length (Lg) is equal to 25 nm. GIDL is reduced by using gradual and offset S/D profile while degradation of drive current is minimized. Through the optimization of lateral straggle and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10 nm fin width.

High velocity of more than 20 m/sec and moving direction are measured by using differential signal process. Principles of operation and basic data are presented.

A three-dimensional mesh generation method in which triangulation of the domain boundary is performed first is desirable since such a method would make it easier to achieve the requirements for the mesh around the boundary. We have developed a mesh generator for a 3D device simulator based on this approach. This mesh generator recursively subdivides a box that includes the whole domain into smaller boxes (cells), a method known as the octree technique. Although our mesh generator is similar to previously reported mesh generators in the sense that it utilizes recursive subdivision of elements, its major difference is that it constructs a triangular mesh upon boundaries of the domain first and this triangular mesh is not changed in the following processes. In order to generate a mesh suitable for the control volume method, a "forbidden region" is introduced and mesh points in the domain are allocated outside of this region. Since the triangular mesh is determined prior to tessellation of the domain, this method is suitable for handling layered mesh along the boundary, which is often necessary to estimate large flows parallel to the boundary precisely. A simple method to provide a layered mesh for a planar boundary is incorporated into the mesh generator. This mesh generator is integrated within our in-house three-dimensional device simulation system. The simulator's practicality is demonstrated through analysis of the reverse narrow channel effect for MOSFETs with LOCOS isolation structures. The effect of protection of the boundary by the layered mesh is also examined by calculating Id-Vg characteristics of a MOSFET with an oblique Si surface, and it is shown that protection of the whole surface of the channel region is necessary to estimate drain current correctly.

In order to achieve an efficient and reliable prediction of device performance by numerical device simulation, a discretization mesh must be generated with an adequate, but not redundant, density of mesh points. However, manual mesh optimization requires user's trial and error. This task annoys the user considerably, especially when the device operation is not well known, or the required mesh-point density strongly depends on the bias condition, or else the manipulation of the mesh is difficult as is expected in 3D. Since these situations often happen in designing advanced VLSI devices, it is highly desirable to automatically optimize the mesh. Adaptive meshing techniques realize automatic optimization by refining the mesh according to the discretization error estimated from the solution. The performance of mesh optimization depends on a posteriori error indicators adopted to evaluate the discretization error. In particular, to obtain a precise terminal-current value, a reliable error indicator for the current continuity equation is necessary. In this paper, adaptive meshing based on the current continuity equation is investigated. A heuristic error indicator is proposed, and a methodology to extend a theoretical error indicator proposed for the finite element method to the requirements of device simulation is presented. The theoretical indicator is based on the energy norm of the flux-density error and is applicable to both Poisson and current continuity equations regardless of the mesh-element shape. These error indicators have been incorporated into the adaptive-mesh device-simulator HFIELDS, and their practicality is examined by MOSFET simulation. Both indicators can produce a mesh with sufficient node density in the channel region, and precise drain current values are obtained on the optimized meshes. The theoretical indicator is superior because it provides a better optimization performance, and is applicable to general mesh elements.

The change of luminance of AC powder electroluminescent panels with temperature has been improved by controlling temperature dependence of impedance of the panels' insulating layer.

A realistic 3-D process/device simulation method was developed for investigating the fluctuation in device characteristics induced by the statistical nature of the number and position of discrete dopant atoms. Monte Carlo procedures are applied for both ion implantation and dopant diffusion/activation simulations. Atomistic potential profile for device simulation is calculated from discrete dopant atom positions by incorporating the long-range part of Coulomb potential. This simulation was used to investigate the variations in characteristics of sub-100 nm CMOS devices induced by realistic dopant fluctuations considering practical device fabrication processes. In particular, sensitivity analysis of the threshold voltage fluctuation was performed in terms of the independent dopant contribution, such as that of the dopant in the source/drain or channel region.

This paper presents advantages of sputtering technique using a ceramic target instead of a conventional powder target for preparing ZnS: TbFx emitting layer in electroluminescent devices.