This paper evaluates impact of self-heating in wire interconnection on signal propagation delay in an upcoming 32 nm process technology, using practical physical parameters. This paper examines a 64-bit data transmission model as one of the most heating cases. Experimental results show that the maximum wire temperature increase due to the self-heating appears in the case where the ratio of interconnect delay becomes largest compared to the driver delay. However, even in the most significant case which induces the maximum temperature rise of 11.0, the corresponding increase in the wire resistance is 1.99% and the resulting delay increase is only 1.15%, as for the assumed 32 nm process. A part of the impact reduction of wire self-heating on timing comes from the size-effect of nano-scale wires.

Two new types of biquadratic active RC filters are presented. The Q sensitivities of the filters with respect to the passive elements can be made zero. The filter structures are canonic. The amplifier gains required are moderate values.

This letter proposes a design methodology of a capacitor for a switched capacitor filter. The capacitor design method makes the capacitor accurate to the capacitance ratio and insensitive to the process deviation. The SCF designed is used for the PCM CODEC filter and the deviation of the frequency characteristic is below 0.05 dB for a process deviation 0.5 µm in 5 µm CMOS process.

Power supply rejection ratio (PSRR) characteristics of a switched capacitor filter (SCF) is improved when using an equal level diagram design of a leapfrog type filter. By using this design method, it is shown that PSRR of a SCF measured is improved about 20 dB.

Leakage current is an important qualitative metric of LSI (Large Scale Integrated circuit). In this paper, we focus on reduction of leakage current variation under the process variation. Firstly, we derive a set of quadratic equations to evaluate delay and leakage current under the process variation. Using these equations, we discuss the cases of varying leakage current without degrading delay distribution and propose a procedure to reduce the leakage current variations. From the experiments, we show the proposed method effectively reduces the leakage current variation up to 50% at 90 percentile point of the distribution compared with the conventional design approach.