An architecture for a high-density nonvolatile memory with ferroelectric capacitors is proposed and simulated. The architecture includes: (1) the operation procedure for DRAM-like memory cells with a Vcc/2 common plate, (2) commands and pin arrangement compatible with those of DRAMs. The resulting ferroelectric memory is expected to show, in addition to nonvolatility, high performance in terms of speed, active power dissipation, and read endurance. In addition, the memory can be handled in the same way as DRAMs. The proposed basic operations are confirmed by using circuit simulations, in which an equivalent circuit model for ferroelectirc capacitors is incorporated. A problem remaining with the architecture is low write endurance due to fatigue along with polarization switching. Designing the reference-voltage generator for 1T1C (one-transistor and one-capacitor) cells, while considering signal reduction along with fatigue, will be another issue for achieving high-density comparable to that of DRAMs.