Half-<I>V<SUB>cc</SUB></I> Plate Nonvolatile DRAMs with Ferroelectric Capacitors

Kan TAKEUCHI; Katsumi MATSUNO; Yoshinobu NAKAGOME; Masakazu AOKI

Half-V_cc Plate Nonvolatile DRAMs with Ferroelectric Capacitors

Kan TAKEUCHI, Katsumi MATSUNO, Yoshinobu NAKAGOME, Masakazu AOKI

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An architecture for a high-density nonvolatile memory with ferroelectric capacitors is proposed and simulated. The architecture includes: (1) the operation procedure for DRAM-like memory cells with a V_cc/2 common plate, (2) commands and pin arrangement compatible with those of DRAMs. The resulting ferroelectric memory is expected to show, in addition to nonvolatility, high performance in terms of speed, active power dissipation, and read endurance. In addition, the memory can be handled in the same way as DRAMs. The proposed basic operations are confirmed by using circuit simulations, in which an equivalent circuit model for ferroelectirc capacitors is incorporated. A problem remaining with the architecture is low write endurance due to fatigue along with polarization switching. Designing the reference-voltage generator for 1T1C (one-transistor and one-capacitor) cells, while considering signal reduction along with fatigue, will be another issue for achieving high-density comparable to that of DRAMs.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.2 pp.234-242

Publication Date: 1996/02/25

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Type of Manuscript: PAPER

Category: Integrated Electronics

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Kan TAKEUCHI, Katsumi MATSUNO, Yoshinobu NAKAGOME, Masakazu AOKI, "Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 2, pp. 234-242, February 1996, doi: .
Abstract: An architecture for a high-density nonvolatile memory with ferroelectric capacitors is proposed and simulated. The architecture includes: (1) the operation procedure for DRAM-like memory cells with a V_cc/2 common plate, (2) commands and pin arrangement compatible with those of DRAMs. The resulting ferroelectric memory is expected to show, in addition to nonvolatility, high performance in terms of speed, active power dissipation, and read endurance. In addition, the memory can be handled in the same way as DRAMs. The proposed basic operations are confirmed by using circuit simulations, in which an equivalent circuit model for ferroelectirc capacitors is incorporated. A problem remaining with the architecture is low write endurance due to fatigue along with polarization switching. Designing the reference-voltage generator for 1T1C (one-transistor and one-capacitor) cells, while considering signal reduction along with fatigue, will be another issue for achieving high-density comparable to that of DRAMs.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e79-c_2_234/_p

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@ARTICLE{e79-c_2_234,
author={Kan TAKEUCHI, Katsumi MATSUNO, Yoshinobu NAKAGOME, Masakazu AOKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors},
year={1996},
volume={E79-C},
number={2},
pages={234-242},
abstract={An architecture for a high-density nonvolatile memory with ferroelectric capacitors is proposed and simulated. The architecture includes: (1) the operation procedure for DRAM-like memory cells with a V_cc/2 common plate, (2) commands and pin arrangement compatible with those of DRAMs. The resulting ferroelectric memory is expected to show, in addition to nonvolatility, high performance in terms of speed, active power dissipation, and read endurance. In addition, the memory can be handled in the same way as DRAMs. The proposed basic operations are confirmed by using circuit simulations, in which an equivalent circuit model for ferroelectirc capacitors is incorporated. A problem remaining with the architecture is low write endurance due to fatigue along with polarization switching. Designing the reference-voltage generator for 1T1C (one-transistor and one-capacitor) cells, while considering signal reduction along with fatigue, will be another issue for achieving high-density comparable to that of DRAMs.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors
T2 - IEICE TRANSACTIONS on Electronics
SP - 234
EP - 242
AU - Kan TAKEUCHI
AU - Katsumi MATSUNO
AU - Yoshinobu NAKAGOME
AU - Masakazu AOKI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 1996
AB - An architecture for a high-density nonvolatile memory with ferroelectric capacitors is proposed and simulated. The architecture includes: (1) the operation procedure for DRAM-like memory cells with a V_cc/2 common plate, (2) commands and pin arrangement compatible with those of DRAMs. The resulting ferroelectric memory is expected to show, in addition to nonvolatility, high performance in terms of speed, active power dissipation, and read endurance. In addition, the memory can be handled in the same way as DRAMs. The proposed basic operations are confirmed by using circuit simulations, in which an equivalent circuit model for ferroelectirc capacitors is incorporated. A problem remaining with the architecture is low write endurance due to fatigue along with polarization switching. Designing the reference-voltage generator for 1T1C (one-transistor and one-capacitor) cells, while considering signal reduction along with fatigue, will be another issue for achieving high-density comparable to that of DRAMs.
ER -