This paper describes ILS (Inter-frame Link Signaling) that provides SDH/SONET (Synchronous Digital Hierarchy/Synchronous Optical NETwork) compatible OAM&P (Operations, Administration, Maintenance, and Provisioning) functions for 10 GbE (10-Gbit/s Ethernet) physical layer links. ILS transports OAM&P overhead bytes by replacing Idles in interframe gaps and organizes virtual frames to emulate SDH/SONET overhead transport. The ILS coding scheme has three features: 10 GbE PHY transparency, error detection ability, and disparity neutral characteristics. A 10 GbE LAN-PHY media converter, one-chip PHY LSI, and a XENPAK transceiver embedded with ILS have been developed in order to facilitate ILS implementation in optical network systems or Ethernet equipment. We confirmed ILS's feasibility through an experiment using the media converters and XENPAKs. The ILS can achieve highly reliable and cost-effective 10 GbE transport over optical networks.

In this paper, a post-layout optimization technique for power dissipation and timing of cell-based Bipolar ECL LSIs is proposed. An ECL LSI can operate at a frequency of a few GHz but the power dissipation is very high compared to CMOS LSIs, which makes the systems using ECL quite expensive. Therefore it is crucial to develop of CAD techniques that minimize the power dissipation of an ECL LSI without decreasing its performance. To begin with, power and delay models of an ECL gate are presented as functions of its switching current. The power dissipation is a linear function of the switching current and the delay time is its hyperbolic function. These functions are obtained considering the post-layout interconnect capacitance and resistance to make the optimization results accurate enough. Using the delay model, a set of timing constraints specifying the max/min cell delay and the clock skew are extracted. This set of constraints in then given to a nonlinear programming package. The objective functions are clock skew time, the clock cycle time and the power dissipation, which are optimized in this order. With the minimum delay and hold constraints, the problem is not convex so that conventional convex programming approach cannot be used. As a result of the optimization, the switching currents for cells are obtained. These are realized within cells by regulating programmable resistors", which is a special feature of our ECL cell library. Since the above optimization is carried out after the placement and routing of the circuit, it can take accurate delay and power estimation into consideration. Experimental results show more than 40% power reductions for circuits including a real communication system chip, compared to the max power versions. The clock cycle time was maintained or even made faster due to the efficient clock skew optimization.

A computer-aided low-power design methodology for very high-speed Si bipolar standard cell LSI is described. In order to obtain Gbit/s-speed operation, it features a pair of differential clock channels inside cells and a highly accurate static timing analysis for back annotation. A newly developed CAD-based power optimization scheme minimizes cell currents while maintaining circuit speed. A 5.6 k gate SDH signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design technology.