A CAD-Based Low-Power Design Methodology for Very High-Speed Si Bipolar Standard Cell LSIs

Keiichi KOIKE; Kenji KAWAI; Akira ONOZAWA; Yuichiro TAKEI; Yoshiji KOBAYASHI; Haruhiko ICHINO

A CAD-Based Low-Power Design Methodology for Very High-Speed Si Bipolar Standard Cell LSIs

Keiichi KOIKE, Kenji KAWAI, Akira ONOZAWA, Yuichiro TAKEI, Yoshiji KOBAYASHI, Haruhiko ICHINO

Full Text Views

0

Share
Cite this

Summary :

A computer-aided low-power design methodology for very high-speed Si bipolar standard cell LSI is described. In order to obtain Gbit/s-speed operation, it features a pair of differential clock channels inside cells and a highly accurate static timing analysis for back annotation. A newly developed CAD-based power optimization scheme minimizes cell currents while maintaining circuit speed. A 5.6 k gate SDH signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design technology.

Publication: IEICE TRANSACTIONS on Electronics Vol.E80-C No.12 pp.1578-1585

Publication Date: 1997/12/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)

Category

Cite this

Copy

Keiichi KOIKE, Kenji KAWAI, Akira ONOZAWA, Yuichiro TAKEI, Yoshiji KOBAYASHI, Haruhiko ICHINO, "A CAD-Based Low-Power Design Methodology for Very High-Speed Si Bipolar Standard Cell LSIs" in IEICE TRANSACTIONS on Electronics, vol. E80-C, no. 12, pp. 1578-1585, December 1997, doi: .
Abstract: A computer-aided low-power design methodology for very high-speed Si bipolar standard cell LSI is described. In order to obtain Gbit/s-speed operation, it features a pair of differential clock channels inside cells and a highly accurate static timing analysis for back annotation. A newly developed CAD-based power optimization scheme minimizes cell currents while maintaining circuit speed. A 5.6 k gate SDH signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design technology.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e80-c_12_1578/_p

Copy

@ARTICLE{e80-c_12_1578,
author={Keiichi KOIKE, Kenji KAWAI, Akira ONOZAWA, Yuichiro TAKEI, Yoshiji KOBAYASHI, Haruhiko ICHINO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A CAD-Based Low-Power Design Methodology for Very High-Speed Si Bipolar Standard Cell LSIs},
year={1997},
volume={E80-C},
number={12},
pages={1578-1585},
abstract={A computer-aided low-power design methodology for very high-speed Si bipolar standard cell LSI is described. In order to obtain Gbit/s-speed operation, it features a pair of differential clock channels inside cells and a highly accurate static timing analysis for back annotation. A newly developed CAD-based power optimization scheme minimizes cell currents while maintaining circuit speed. A 5.6 k gate SDH signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design technology.},
keywords={},
doi={},
ISSN={},
month={December},}

Copy

TY - JOUR
TI - A CAD-Based Low-Power Design Methodology for Very High-Speed Si Bipolar Standard Cell LSIs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1578
EP - 1585
AU - Keiichi KOIKE
AU - Kenji KAWAI
AU - Akira ONOZAWA
AU - Yuichiro TAKEI
AU - Yoshiji KOBAYASHI
AU - Haruhiko ICHINO
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1997
AB - A computer-aided low-power design methodology for very high-speed Si bipolar standard cell LSI is described. In order to obtain Gbit/s-speed operation, it features a pair of differential clock channels inside cells and a highly accurate static timing analysis for back annotation. A newly developed CAD-based power optimization scheme minimizes cell currents while maintaining circuit speed. A 5.6 k gate SDH signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design technology.
ER -