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Katsuyuki SATO Masahiro OGATA Miki MATSUMOTO Ryouta HAMAMOTO Kiichi MANITA Terutaka OKADA Yuji SAKAI Kanji OISHI Masahiro YAMAMURA
Four circuit techniques and a layout design scheme were proposed to realize a 2 Mb VRAM used 0.8 µm technology. They are the enhanced circuit technologies for high speed operation, the functional circuit design and the effective repair schemes for a VRAM, the low power consumption techniques to active and standby mode and a careful layout design scheme realizing high noise immunity. Using these design techniques, a 2 Mb VRAM is suitable for the graphics application of a 5125128 pixels basis screen, with a clear mode of 4.6 GByte/sec and a 4-multi column write mode of 400 MByte/sec, even using the same 0.8 µm technology as the previous VRAM (1 Mb) was realized.