A high efficiency feedforward power amplifier (FFPA) with a series diode linearizer for cellular base stations is presented. In order to achieve the highest overall efficiency of an FFPA, an improved pre-distortion diode linearizer has been used and the bias condition of the main amplifier has been optimized. The optimum bias condition has been derived from the overall efficiency analysis of the FFPA with a pre-distortion linearizer. From measured overall performances of the FFPA, efficiency enhancement of the series diode linearizer has been verified. The developed FFPA achieved the efficiency of 10% and output power of 45.6 dBm at 10 MHz offset Adjacent Channel leakage Power Ratio (ACPR) -50 dBc under Wide-band Code-Division Multiple-Access (W-CDMA) modulated 2 carriers signal. This design method can be also used to optimize the source and load impedances condition of the main amplifier FET.

As microprocessor units have become faster, DRAMs have also been required to become faster. One of the fast DRAMs is the synchronous DRAM, which transfers data at a high rate. We have developed a 100-MHz Synchronous DRAM using pipeline architecture and new high speed I/O lines method. This paper describes some features of the DRAM and its new pipeline architecture.

In this paper, we consider the behavior of an autoregressive (AR) detector for partial-response (PR) signaling against offtrack interference (OTI) environment in perpendicular magnetic recording. Based on the behavior, we derive the optimum branch metric to construct the detector by the Viterbi algorithm. We propose an optimum AR detector for OTI that considers an optimum branch metric calculation and an estimation of noise power due to OTI in order to calculate an accurate branch metric. To evaluate the reliability of soft-output likelihood values calculated by our proposed AR detector, we demonstrate a bit error rate performance (BER) of low-density parity-check (LDPC) codes under OTI existing channel by computer simulation. Our simulation results show the proposed AR detector can achieve a better LDPC-coded BER performance than the conventional AR detector. We also show the BER performance of our proposal can keep within 0.5 dB of the case that perfect channel state information regarding OTI is used in the detector. In addition, we show that the partial-response maximum-likelihood (PRML) detector is robust against OTI even if OTI is not handled by the detector.

Four circuit techniques and a layout design scheme were proposed to realize a 2 Mb VRAM used 0.8 µm technology. They are the enhanced circuit technologies for high speed operation, the functional circuit design and the effective repair schemes for a VRAM, the low power consumption techniques to active and standby mode and a careful layout design scheme realizing high noise immunity. Using these design techniques, a 2 Mb VRAM is suitable for the graphics application of a 5125128 pixels basis screen, with a clear mode of 4.6 GByte/sec and a 4-multi column write mode of 400 MByte/sec, even using the same 0.8 µm technology as the previous VRAM (1 Mb) was realized.