Four circuit techniques and a layout design scheme were proposed to realize a 2 Mb VRAM used 0.8 µm technology. They are the enhanced circuit technologies for high speed operation, the functional circuit design and the effective repair schemes for a VRAM, the low power consumption techniques to active and standby mode and a careful layout design scheme realizing high noise immunity. Using these design techniques, a 2 Mb VRAM is suitable for the graphics application of a 5125128 pixels basis screen, with a clear mode of 4.6 GByte/sec and a 4-multi column write mode of 400 MByte/sec, even using the same 0.8 µm technology as the previous VRAM (1 Mb) was realized.

As microprocessor units have become faster, DRAMs have also been required to become faster. One of the fast DRAMs is the synchronous DRAM, which transfers data at a high rate. We have developed a 100-MHz Synchronous DRAM using pipeline architecture and new high speed I/O lines method. This paper describes some features of the DRAM and its new pipeline architecture.