This paper describes a sub 1-V low noise amplifier (LNA) fabricated using a 0.35 µm SOI (silicon on insulator) CMOS process. The SOI devices have high speed performance even at low operating voltage (below 1 V) because of their smaller parasitic capacitance at source and drain than those of bulk MOSs. A body of a MOSFET can be controlled by using a field shield (FS) plate. The transistor body of the LNA is connected to its gate. The threshold voltage of the transistor becomes lower due to the body-biased effect so that a large drain current keeps the gain high, and active-body control improves the 1-dB gain compression point. A gain of 7.0 dB and a Noise Figure (NF) of 3.6 dB are obtained at 1.0 V and 1.9 GHz. The output power at the 1-dB gain compression point is +1.5 dBm. The gain and the output power at the 1-dB gain compression point are higher by 1.2 dB and 2.9 dB respectively than those of a conventionally body-fixed LNA. A 5.5 dB gain is also obtained at the supply voltage of 0.5 V.

This paper describes 2.4-GHz-band front-end building circuits--a down conversion mixer (DCM), a dual-modulus divide-by-4/5 prescaler, a transmit/receive antenna switch (SW), a power amplifier (PA), and a low noise amplifier (LNA). They are fabricated using a standard bulk 0.18 µm CMOS process with a lower current consumption than bipolar circuits, and can operate at the low supply voltage of 1.8 V. Meshed-shielded pads are adopted for lower receiver circuit noise. Pads shielded by metals become cracked when they are bounded, therefore silicided active areas are used as shields instead of metals to avoid these cracks. The meshed shields achieve lower parasitic pad capacitors without parasitic resistors, and also act as dummy active areas. The proposed DCM has a high IP3 characteristic. The DCM has a cascode FET configuration and LO power is injected into the lower FET. By keeping the drain-source voltage of the upper transistor large, the nonlinearity of the drain-source transconductance is reduced and a low distortion DCM is realized. It achieves a higher input referred IP3 with a higher conversion gain for almost the same current consumption of a conventional single-balanced mixer. The output referred IP3 is higher 5.0 dB than the single-balanced mixer. The proposed dual-modulus prescaler employs a fully-differential technique to achieve stable operation. In order to avoid errors, the fully-differential circuit gives the logic voltage swing margins. In addition, the differential technique also reduces the noise effect from the supply voltage line because of the common-mode signal rejection. The maximum operating frequency is 3.0 GHz, and the one flip-flop power consumption normalized by the maximum operating frequency is 180 µW/GHz.

This paper describes a single-chip RF transce-iver LSI for 2.4-GHz-band Bluetooth applications. This chip uses a 0.5 µm BiCMOS process, which provides 23 GHz fT. The LSI consists of almost all the required RF and IF building blocks--a power amplifier (PA), a low noise amplifier (LNA), an image rejection mixer (IRM), channel-selection filters, a limiter, a received signal strength indicator (RSSI), a frequency discriminator, a voltage controlled oscillator (VCO), and a phase-locked loop (PLL) synthesizer. The transceiver consumes 34.4 mA in TX mode (PA, VCO, PLL) and 44.0 mA in RX mode (LNA, IRM, channel-selection filters, limiter, RSSI, frequency discriminator, VCO, PLL). Direct-up conversion with a frequency doubler is used for the TX architecture. In order to avoid the VCO pulling, we used a 1.2 GHz VCO with the frequency doubler. In the receiver section, a low-IF single conversion RX architecture is employed for the integration of the channel-selection filters. The transceiver has a proposed linear frequency discriminator with a wide input range. The wide input-frequency range discriminator is required to realize the lower IF RX architecture because of the higher ratio of frequency deviation to the center IF frequency. The discriminator is the delay line type, and consists of a mixer and a delay line circuit with a locked loop. The delay line connects to one input terminal of the mixer. By using the delay locked at one fourth of the period of the IF frequency, a quadrature phase shift IF signal is applied to the mixer input terminal. For the frequency discriminator, the DC output voltage changes in proportion to the input frequency and a wide input range is achieved. This RF transceiver sufficiently satisfies all the target specifications for short-range Bluetooth applications. By using this chip, a -80 dBm sensitivity is obtained for the 10-3 BER, and the transceiver can deliver an output power of over 0.0 dBm.

This paper describes two kinds of on-chip matched low-noise/driver MMIC amplifiers (LN/D-As) suitable for 2.4-GHz and 5.2-GHz short-range wireless applications. The ICs are fabricated in a 0.18 µm bulk CMOS which has no extra processing steps for enhancing the RF performance. The successful use of the current-reuse topology and interdigitated capacitors (IDCs) enables sufficiently low-noise and high output power operations with low current dissipation despite the chip fabrication in the bulk CMOS leading to large RF substrate and conductor losses. The main measurement results of the two LN/D-As are as follows: a 3.8-dB noise figure (NF) and a 10.1-dB gain under the conditions of 1.8 V and 6 mA, a 3.4-dBm 1-dB gain compressed output power (P1dB) for a 2.4-V voltage supply and a 13-mA operating current for the 2.4-GHz LN/D-A, and a 4.9-dB NF and an 11.1-dB gain with a 1.8 V and 10 mA supply condition, a 2.3-dBm P1dB at 2.4 V and 16 mA for the 5.2-GHz LN/D-A. Both MMICs are suited for low-noise amplifiers and driver amplifiers in 2.4-GHz and 5.2-GHz low-cost, low-power wireless systems such as Bluetooth and hiperLAN.