A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS

Sho IKEDA; Sangyeop LEE; Tatsuya KAMIMURA; Hiroyuki ITO; Noboru ISHIHARA; Kazuya MASU

doi:10.1587/transele.E97.C.495

A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS

Sho IKEDA, Sangyeop LEE, Tatsuya KAMIMURA, Hiroyuki ITO, Noboru ISHIHARA, Kazuya MASU

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This paper proposes an ultra-low-power 5.5-GHz PLL which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO with linearity-compensated varactor for low supply voltage operation. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The FBB is also employed for linear-frequency-tuning of VCO under low supply voltage of 0.5V. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The digital calibration circuit is introduced to control the lock-range of ILFD automatically. The proposed PLL was fabricated in a 65nm CMOS process. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106dBc/Hz at 5.5GHz output. The supply voltage is 0.54V for divider and 0.5V for other components. Total power consumption is 0.95mW.

Publication: IEICE TRANSACTIONS on Electronics Vol.E97-C No.6 pp.495-504

Publication Date: 2014/06/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E97.C.495

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)

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Authors

Sho IKEDA
  Tokyo Institute of Technology
Sangyeop LEE
  Tokyo Institute of Technology
Tatsuya KAMIMURA
  Tokyo Institute of Technology
Hiroyuki ITO
  Tokyo Institute of Technology
Noboru ISHIHARA
  Tokyo Institute of Technology
Kazuya MASU
  Tokyo Institute of Technology

Keyword

injection-locked frequency divider, phase-locked loop, Class-C VCO, CMOS, low supply voltage

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Sho IKEDA, Sangyeop LEE, Tatsuya KAMIMURA, Hiroyuki ITO, Noboru ISHIHARA, Kazuya MASU, "A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS" in IEICE TRANSACTIONS on Electronics, vol. E97-C, no. 6, pp. 495-504, June 2014, doi: 10.1587/transele.E97.C.495.
Abstract: This paper proposes an ultra-low-power 5.5-GHz PLL which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO with linearity-compensated varactor for low supply voltage operation. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The FBB is also employed for linear-frequency-tuning of VCO under low supply voltage of 0.5V. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The digital calibration circuit is introduced to control the lock-range of ILFD automatically. The proposed PLL was fabricated in a 65nm CMOS process. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106dBc/Hz at 5.5GHz output. The supply voltage is 0.54V for divider and 0.5V for other components. Total power consumption is 0.95mW.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E97.C.495/_p

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@ARTICLE{e97-c_6_495,
author={Sho IKEDA, Sangyeop LEE, Tatsuya KAMIMURA, Hiroyuki ITO, Noboru ISHIHARA, Kazuya MASU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS},
year={2014},
volume={E97-C},
number={6},
pages={495-504},
abstract={This paper proposes an ultra-low-power 5.5-GHz PLL which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO with linearity-compensated varactor for low supply voltage operation. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The FBB is also employed for linear-frequency-tuning of VCO under low supply voltage of 0.5V. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The digital calibration circuit is introduced to control the lock-range of ILFD automatically. The proposed PLL was fabricated in a 65nm CMOS process. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106dBc/Hz at 5.5GHz output. The supply voltage is 0.54V for divider and 0.5V for other components. Total power consumption is 0.95mW.},
keywords={},
doi={10.1587/transele.E97.C.495},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 495
EP - 504
AU - Sho IKEDA
AU - Sangyeop LEE
AU - Tatsuya KAMIMURA
AU - Hiroyuki ITO
AU - Noboru ISHIHARA
AU - Kazuya MASU
PY - 2014
DO - 10.1587/transele.E97.C.495
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E97-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2014
AB - This paper proposes an ultra-low-power 5.5-GHz PLL which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO with linearity-compensated varactor for low supply voltage operation. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The FBB is also employed for linear-frequency-tuning of VCO under low supply voltage of 0.5V. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The digital calibration circuit is introduced to control the lock-range of ILFD automatically. The proposed PLL was fabricated in a 65nm CMOS process. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106dBc/Hz at 5.5GHz output. The supply voltage is 0.54V for divider and 0.5V for other components. Total power consumption is 0.95mW.
ER -