An analytic equation was derived for the time jitter of digital NRZ signals due to inter-symbol interference in the PCB transmission lines loaded by DRAM chips which are located in uniform spacing. The inter-symbol interference is caused by a low-pass filtering effect of the loaded transmission line. Good agreements were observed between the equation and measurements with an average error of 17.5%.

A CMOS DFE (decision feedback equalization) receiver with a clock-data skew compensation was implemented for the SSTL (stub-series terminated logic) SDRAM interface. The receiver consists of a 2 way interleaving DFE input buffer for ISI reduction and a X2 over-sampling phase detector for finding the optimum sampling clock position. The measurement results at 1.2 Gbps operation showed the increase of voltage margin by about 20% and the decrease of time jitter in the recovered sampling clock by about 40% by equalization in an SSTL channel with 2 pF 4 stub load. Active chip area and power consumption are 3001000 µm2 and 142 mW, respectively, with a 2.5 V, 0.25 µm CMOS process.

Wide-voltage-range DRAM's with extended data retention are desirable for battery-operated or portable computers and consumer devices. This paper describes the techniques required to obtain wide operation, functionality, and performance of standard DRAM's from 1.8 V (2 NiCd or Alkaline batteries) to 3.6 V (upper end of LVTTL standard). Specific techniques shown are: 1) a low-power and low-voltage reference generator for detecting VCC level; 2) compensation of dc generators, VBB and VPP, for obtaining high speed at reduced voltages; 3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and 4) a programmable VCC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16M DRAM(2M 8) by simulation.