A Decision Feedback Equalizing Receiver for the SSTL SDRAM Interface with Clock-Data Skew Compensation

Young-Soo SOHN; Seung-Jun BAE; Hong-June PARK; Soo-In CHO

A Decision Feedback Equalizing Receiver for the SSTL SDRAM Interface with Clock-Data Skew Compensation

Young-Soo SOHN, Seung-Jun BAE, Hong-June PARK, Soo-In CHO

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A CMOS DFE (decision feedback equalization) receiver with a clock-data skew compensation was implemented for the SSTL (stub-series terminated logic) SDRAM interface. The receiver consists of a 2 way interleaving DFE input buffer for ISI reduction and a X2 over-sampling phase detector for finding the optimum sampling clock position. The measurement results at 1.2 Gbps operation showed the increase of voltage margin by about 20% and the decrease of time jitter in the recovered sampling clock by about 40% by equalization in an SSTL channel with 2 pF 4 stub load. Active chip area and power consumption are 3001000 µm² and 142 mW, respectively, with a 2.5 V, 0.25 µm CMOS process.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.5 pp.809-817

Publication Date: 2004/05/01

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Type of Manuscript: PAPER

Category: Integrated Electronics

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Young-Soo SOHN, Seung-Jun BAE, Hong-June PARK, Soo-In CHO, "A Decision Feedback Equalizing Receiver for the SSTL SDRAM Interface with Clock-Data Skew Compensation" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 5, pp. 809-817, May 2004, doi: .
Abstract: A CMOS DFE (decision feedback equalization) receiver with a clock-data skew compensation was implemented for the SSTL (stub-series terminated logic) SDRAM interface. The receiver consists of a 2 way interleaving DFE input buffer for ISI reduction and a X2 over-sampling phase detector for finding the optimum sampling clock position. The measurement results at 1.2 Gbps operation showed the increase of voltage margin by about 20% and the decrease of time jitter in the recovered sampling clock by about 40% by equalization in an SSTL channel with 2 pF 4 stub load. Active chip area and power consumption are 3001000 µm² and 142 mW, respectively, with a 2.5 V, 0.25 µm CMOS process.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e87-c_5_809/_p

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@ARTICLE{e87-c_5_809,
author={Young-Soo SOHN, Seung-Jun BAE, Hong-June PARK, Soo-In CHO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Decision Feedback Equalizing Receiver for the SSTL SDRAM Interface with Clock-Data Skew Compensation},
year={2004},
volume={E87-C},
number={5},
pages={809-817},
abstract={A CMOS DFE (decision feedback equalization) receiver with a clock-data skew compensation was implemented for the SSTL (stub-series terminated logic) SDRAM interface. The receiver consists of a 2 way interleaving DFE input buffer for ISI reduction and a X2 over-sampling phase detector for finding the optimum sampling clock position. The measurement results at 1.2 Gbps operation showed the increase of voltage margin by about 20% and the decrease of time jitter in the recovered sampling clock by about 40% by equalization in an SSTL channel with 2 pF 4 stub load. Active chip area and power consumption are 3001000 µm² and 142 mW, respectively, with a 2.5 V, 0.25 µm CMOS process.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - A Decision Feedback Equalizing Receiver for the SSTL SDRAM Interface with Clock-Data Skew Compensation
T2 - IEICE TRANSACTIONS on Electronics
SP - 809
EP - 817
AU - Young-Soo SOHN
AU - Seung-Jun BAE
AU - Hong-June PARK
AU - Soo-In CHO
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2004
AB - A CMOS DFE (decision feedback equalization) receiver with a clock-data skew compensation was implemented for the SSTL (stub-series terminated logic) SDRAM interface. The receiver consists of a 2 way interleaving DFE input buffer for ISI reduction and a X2 over-sampling phase detector for finding the optimum sampling clock position. The measurement results at 1.2 Gbps operation showed the increase of voltage margin by about 20% and the decrease of time jitter in the recovered sampling clock by about 40% by equalization in an SSTL channel with 2 pF 4 stub load. Active chip area and power consumption are 3001000 µm² and 142 mW, respectively, with a 2.5 V, 0.25 µm CMOS process.
ER -