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[Author] Suguru TACHIBANA(2hit)
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A 5-mW, 10-ns Cycle TLB Using a High-Performance CAM with Low-Power Match-Detection Circuits
Hisayuki HIGUCHI Suguru TACHIBANA Masataka MINAMI Takahiro NAGANO
- PAPER-Static RAMs
- Vol:
- E79-C No:6
- Page(s):
- 757-762
Low-power, high-speed match-detection circuits for a content addressable memory(CAM) are proposed and evaluated. The circuits consist a current supply to a match-line, a differential amplifier, and 9-MOSFET CAM cells. The implementation of these circuits made it possible to realize a 16-entry, 32-bit data-compare CAM TEG of 1.2-ns matchdetection time with 5-mW power dissipation in 10-ns cycle-time.
A 2.6-ns Wave-Pipelined CMOS SRAM with Dual-Sensing-Latch Circuits
Suguru TACHIBANA Hisayuki HIGUCHI Koichi TAKASUGI Katsuro SASAKI Toshiaki YAMANAKA Yoshinobu NAKAGOME
- PAPER
- Vol:
- E78-C No:6
- Page(s):
- 735-738
The dual-sensing-latch circuit proposed here can solve the synchronization problem of the conventional wave-pipelined SRAM, and the proposed source-biased self-resetting circuit reduces both the cycle and access time of cache SRAM's. A 16-kb SRAM using these circuit techniques was designed, and was fabricated with 0.25-µm CMOS technology. Simulation results indicate that this SRAM has a typical clock access time of 2.6 ns at 2.5-V supply voltage and a worst minimum cycle time of 2.6 ns.
