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Takao KIHARA Tomohiro SANO Masakazu MIZOKAMI Yoshikazu FURUTA Mitsuhiko HOKAZONO Takaya MARUYAMA Tetsuya HEIMA Hisayasu SATO
We present a multiband LTE SAW-less CMOS transmitter with source-follower-driven passive mixers, envelope-tracked RF-programmable gain amplifiers (RF-PGAs), and Marchand Baluns. A driver stage for passive mixers is realized by a source follower, which enables a quadrature modulator (QMOD) to achieve low noise performance at a 1.2 V supply and contributes to a small-area and low-power transmitter. An envelope-tracking technique is adopted to improve the linearity of RF-PGAs and obtain a better Evolved Universal Terrestrial Radio Access Adjacent Channel Leakage power Ratio (E-UTRA ACLR). The Marchand balun covers more frequency bands than a transformer and is more suitable for multiband operation. The proposed transmitter, which also includes digital-to-analog converters and a phase-locked loop, is implemented in a 65-nm CMOS process. The implemented transmitter achieves E-UTRA ACLR of less than -42 dBc and RX-band noise of less than -158 dBc/Hz in the frequency range of 700 MHz–2.6 GHz. These performances are good enough for multiband LTE and SAW-less operation.
Koji TSUTSUMI Takaya MARUYAMA Wataru YAMAMOTO Takanobu FUJIWARA Tatsuya HAGIWARA Ichiro SOMADA Eiji TANIGUCHI Mitsuhiro SHIMOZAWA
A 15GHz-band 4-channel transmit/receive RF core-chip is presented for high SHF wide-band massive MIMO in 5G. In order to realize small RF frontend for 5G base stations, both 6bit phase shifters (PS) and 0.25 dB resolution variable gain amplifiers (VGA) are integrated in TX and RX paths of 4-channels on the chip. A PS calibration technique is applied to compensate the error of 6bit PS caused by process variations. A common gate current steering topology with tail current control is used for VGA to enhance the gain control accuracy. The 15GHz-band RF core-chip fabricated in 65 nm CMOS process achieved phase control error of 1.9deg. rms., and amplitude control error of 0.23 dB. rms.
Hisayasu SATO Takaya MARUYAMA Toshimasa MATSUOKA Kenji TANIGUCHI
This paper presents the design consideration of a four-stage variable gain amplifier (VGA) with a wide dynamic range for receivers. The VGA uses parallel amplifiers for the first and second amplifiers in order to improve the input third-order intercept point (IIP3) in the low gain region. To investigate the behavior of the VGA, the gain and linearity analyses are newly derived for the parallel amplifiers, and are compared with the measured results. In addition, the principle of the temperature compensation is described. The gain control range of 110 dB, the IP1 dB of -11 dBm, and noise figure (NF) of 5.1 dB were measured using a 0.5 µm 26 GHz fT BiCMOS process.