We have studied the electrical and breakdown characteristics of 5 nm-thick HfSiOxNy (Hf/(Hf + Si)=0.43, nitrogen content=4.5-17.8 at.%) in Al-gate and NiSi-gate capacitors. For Al-gate capacitors, the flat-band shift due to positive fixed charges increases with the nitrogen content in the dielectric layer. In contrast, for NiSi-gate capacitors, the flat band is almost independent of the nitrogen content, which is presumably controlled by the quality of the interface between NiSi and the dielectric layer. The leakage current markedly increases with nitrogen content. Correspondingly, although the time-to-soft breakdown, tSBD, gradually decreases with increasing nitrogen content, the charge-to-soft breakdown, QSBD, increases with the nitrogen content. For Al-gate capacitors, the Weibull slope of time-dependent dielectric breakdown (TDDB) under constant voltage stress (CVS) remains constant at 2 for a nitrogen content of up to 12.5 at.% and then decreases to unity at 17.8 at.%. This must be a condition critical to the formation of the percolation path for breakdown. In contrast, for NiSi gate capacitors, a Weibull slope smaller than unity was obtained, suggesting that structural inhomogeneity, involving defect generation, is introduced during the NiSi gate fabrication, but this negative impact is reduced with nitrogen incorporation.

This paper describes the fabrication of 0.1 µm gate length CMOS devices and analysis of delay time by circuit simulation. In order to reduce the gate resistance, TiN capped cobalt salicide technology is applied to the fabrication of 0.1 µm CMOS devices. Gate sheet resistance with a 0.1 µm gate is as low as 5 Ω/sq. Propagation delay times of 0.1 µm and 0.15 µm CMOS inverter are 21 ps and 36 ps. Simulated propagation delay time agreed fairly well with experimental results. For gate length over 0.15 µm, intrinsic delay in CMOS devices is the main dalay factor. This suggests that increasing current drivability is the most efficient way to improve propagation delay time. At 0.1 µm, each parasitic component and intrinsic delay have similar contributions on device speed due to the short channel effect. To improve delay time, we used rapid thermal annealing or a high dose LDD structure. With this structure, drain current increases by more than 1.3 times and simulation predicted a delay time of 28 ps is possible with 0.15 µm CMOS inverters.

Using Ti self-aligned silicide (salicide) process, we fabricated subquarter-micron complementary metal-oxide semiconductor (CMOS) devices, and studied the mechanism of increasing resistivity of TiSi2 on poly-Si gates from 0.075 to 20 µm long and 10 µm wide. In the gates less than 0.1 µm long, we found that agglomeration of TiSi2 takes place during low temperature annealing at 675 for 30 seconds leading to discontinuous TiSi2 lines. The discontinuity of TiSi2 abruptly increases the gate resistance, and remarkably reduces the circuit speed of CMOS ring oscillators. On the other hand, Raman spectroscopy reveals that the phase transition from high-resistivity C49 to low-resistivity C54 occurs in plane TiSi2 by annealing at 800 for 30 seconds, while it does not occur in TiSi2 gates less than 5 µm long. From these results we found that the gate sheet resistance can not be reduced to less than 5 Ω/sq by conventional Ti salicide technology in gates shorter than 0.4 µm due to increase in gate resistance caused by agglomeration and lack of phase transition.