This paper describes high-temperature operation of nMOSFET on bonded SOI. A long-channel nMOSFET is fabricated on bonded SOI (Si layer thickness 0.3 µm), SOS (Si layer thickness 0.3 µm), and bulk Si, Bonded SOI is produced using pulse-field-assisited bonding and resistivity-sensitive etching. The high-temperature operation of bonded SOI nMOSFET is demonstrated and compared with SOS and bulk MOSFETs. The leakage current variation with temperature is signnificantly smaller in bonded SOI and in SOS than in bulk MOSFETs. At high temperatures, the drain current to leakage current ratio is 100 times higher in bonded SOI than in SOS and bulk devices. At 300, a ratio of 104 is obtained for the bonded SOI nMOSFET. The ratio is expected to be even higher if a reduced channel length and ultrathin (less than 0.1 µm) bonded SOI is used.

We propose a high-speed SOI bipolar transistor fabricated using bonding and thinning techniques. It is important to replace SOI area except for devices with thick SiO2 to reduce parasitic capacitance. A thin SOI film with a thin buried layer helps meet this requirement. We formed a 1-µm-thick SOI film with a 0.7-µm-thick buried layer by ion implantation before wafer bonding pulse-field-assisted bonding and selective polishing. Devices were completely isolated by thick SiO2 using a thin SOI film and the LOCOS process. We fabricated epitaxial base transistors (EBTs) on bonded SOI. Our transistors had a cutoff frequency of 32 GHz.

We fabricated a 4 GHz thin-base (120 nm) lateral bipolar transistor on bonded SOI by applying our sidewall self-aligning base process. By applying this device to BiCMOS circuits, bipolar transistor base junction capacitance, and MOSFET source and drain capacitance were very small. Furthermore, MOSFET and bipolar transistors are completely isolated from each other. Thus, it is easy to optimize MOS and bipolar processes, and provide protection from latch-up problems and soft errors caused by α-particles. In this paper, we describe device characteristics and discuss the crystal quality degradation introduced by ion implantation, and two dimensional effects of base diffusion capacitance.

Using Ti self-aligned silicide (salicide) process, we fabricated subquarter-micron complementary metal-oxide semiconductor (CMOS) devices, and studied the mechanism of increasing resistivity of TiSi2 on poly-Si gates from 0.075 to 20 µm long and 10 µm wide. In the gates less than 0.1 µm long, we found that agglomeration of TiSi2 takes place during low temperature annealing at 675 for 30 seconds leading to discontinuous TiSi2 lines. The discontinuity of TiSi2 abruptly increases the gate resistance, and remarkably reduces the circuit speed of CMOS ring oscillators. On the other hand, Raman spectroscopy reveals that the phase transition from high-resistivity C49 to low-resistivity C54 occurs in plane TiSi2 by annealing at 800 for 30 seconds, while it does not occur in TiSi2 gates less than 5 µm long. From these results we found that the gate sheet resistance can not be reduced to less than 5 Ω/sq by conventional Ti salicide technology in gates shorter than 0.4 µm due to increase in gate resistance caused by agglomeration and lack of phase transition.

A behavioral model for ferroelectric capacitors is developed. There are two requirements for the circuit simulation model; one is to reproduce the hysteretic behavior of the polarization under arbitrary voltage history, and the other is to describe the time dependence of polarization change. A parallel element model has been proposed to meet the first requirement. This model reproduces the minor loops of the hysteresis by assuming that the ferroelectric capacitor consists of the parallel capacitors of different polarization and coercive voltages. In order to add the function to describe the time dependence of the polarization change, we propose a method of measuring the switching response for individual parallel elements and the model which describes the response. In the measurement, the voltage applied to the capacitor is raised in two steps. After the first step, the voltage is kept at an intermediate level for a period of time, then raised again to the final level and the polarization change was recorded as a function of time. Because the capacitor elements with the coercive voltage lower than the intermediate level complete switching during the first step, the polarization change of the whole capacitor during the second step is attributed to the capacitor elements with the coercive voltage higher than the intermediate level. This procedure is repeated with changing the intermediate level, and the switching response of each capacitor element is obtained by taking the finite differences between the adjacent sets of data. The measurement on a sol-gel derived SrBi2Ta2O9 capacitor revealed that the switching time depended only on the difference between the applied voltage and the coercive voltage of each capacitor element. The time dependence of the polarization change is implemented to the model by inserting a nonlinear resistor in series with each capacitor, which reproduces the polarization switching under arbitrary voltage change without any fitting parameters.