A Unique word-line voltage control method for the 64-Mb DRAM and beyond, which realizes a constant lifetime for thin gate oxide, is proposed. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps constant time-dependent dielectric breakdown (TDDB) lifetime, under any conditions concerning gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 105 times reliability improvement, or a 0.3 1.8-V larger word-line voltage margin to write ONE data into the cell.

This paper describes fault-tolerant designs, which have been used to boost the yield of a 286 mm2 256 Mb DRAM with 32 both-ends DQ. The 256 Mb DRAM consists of sixteen 16 Mb units, each containing one 128 Kb row redundancy block. This row redundancy block architecture allows flexible row redundancy replacement, where random faults, clustered faults, and grouped faults can be efficiently repaired. Flexible column redundancy replacement with interchangeable master DQ's(MDQ) is used to allow a 256 b data compression without causing a data conflict, while improving the column access speed by 2 ns. A depletion NMOS bitline-precharge-current-limiter suppresses the current flow which occursas a result of a wordlinebitline short-circuit to only 15 µA per cross fail, avoiding a standby current fail. Consequently, the hardware results show a significant yield enhancement of 16 times relative to the intrablock/segment replacement. Detailed simulation results show that this 256 Mb DRAM allows 275 random faults to be repaired with 5.5% silicon area overhead for 80% chip yield.

This paper descriles a 256 Mb DRAM chip architecture which provides up to 32 wide organization. In order to minimize the die sixe, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25µmCMOS technology. The chip measures 13.25mm21.55mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe(RAS) access time of 26 ns was obtained under 2.8 V power supply and 85 . In addition, a 100 MHz32 page mode operation, namely 400 M byte/s data rate, in the standard extended data output(EDO) cycle has been succssfully demonstrated.