In order to achieve 3.3-V 1-Gb DRAM and beyond, this paper proposes a new on-chip supply voltage conversion scheme, which converts 3.3-V external supply voltage Vext to lowered 1.5-V internal supply voltage Vint without any power loss within the voltage converter. This scheme connects two identical DRAM circuits in series between Vext and Vss. By operations of two DRAM circuits with the same clock timing, the voltage between two DRAM's, Vint, is automatically fixed to 1/2Vext. Therefore, each upper and lower DRAM circuit can operate at lowered 1/2Vext without use of the conventional voltage converter. This scheme was successfully verified by an experimental system using 4-Mb DRAM's. Utilizing the proposed scheme, power dissipation was reduced by as much as 50% and stable operation was achieved without access speed penalty.

This paper descriles a 256 Mb DRAM chip architecture which provides up to 32 wide organization. In order to minimize the die sixe, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25µmCMOS technology. The chip measures 13.25mm21.55mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe(RAS) access time of 26 ns was obtained under 2.8 V power supply and 85 . In addition, a 100 MHz32 page mode operation, namely 400 M byte/s data rate, in the standard extended data output(EDO) cycle has been succssfully demonstrated.