Key fabrication technology for the Pt/TiO2-x/TiO2/TiO2+x/Pt nano-film memristor is investigated, including preparing platinum (Pt) electrodes and TiO2-x/TiO2/TiO2+x nano-films. The effect of oxygen flow rate and deposition rate during fabrication on O:Ti ratio of thin films is demonstrated. The fabricated nano-films with different oxygen concentration are validated by the analyzed results from X-ray photoelectron spectroscopy (XPS). The obtained memristor device shows the typical resistive switching behavior and nonvolatile memory effects. An analytical device model for Pt/TiO2-x/TiO2/TiO2+x/Pt nano-film memristor is developed based on the fundamental linear relationships between drift-diffusion velocity and the electric field, and boundary conditions are also incorporated in this model. This model is able to predict the relation between variables in the form of explicit formula, which is very critical in memristor-based circuit designs. The measurement results from real devices validate the proposed analytical device model. Some deviations of the model from the measured data are also analyzed and discussed.

Emerging video surveillance technologies are based on foreground detection to achieve event detection automatically. Integration foreground detection with a modern multi-camera surveillance system can significantly increase the surveillance efficiency. The foreground detection often leads to high computational load and increases the cost of surveillance system when a mass deployment of end cameras is needed. This paper proposes a DSP-based foreground detection algorithm. Our algorithm incorporates a temporal data correlation predictor (TDCP) which can exhibit the correlation of data and reduce computation based on this correlation. With the DSP-oriented foreground detection, an adaptive frame rate control is developed as a low cost solution for multi-camera surveillance system. The adaptive frame rate control automatically detects the computational load of foreground detection on multiple video sources and adaptively tunes the TDCP to meet the real-time specification. Therefore, no additional hardware cost is required when the number of deployed cameras is increased. Our method has been validated on a demonstration platform. Performance can achieve real-time CIF frame processing for a 16-camera surveillance system by single-DSP chip. Quantitative evaluation demonstrates that our solution provides satisfied detection rate, while significantly reducing the hardware cost.

This paper studies the optimization of the effective channel capacity of wideband code division multiple access (WCDMA) systems under Rayleigh fading environments. Firstly, the results for Shannon capacity of fading channels with channel side information are reviewed, where the capacity is achieved by using an optimal power control scheme. Secondly, an optimal interference threshold is set for a given system outage probability Pout to minimize total interference. Finally, the effective channel capacity of WCDMA is defined and a target SIR level γ* is derived with the Lagrangian multiplier method to maximize the effective channel capacity. It is shown that is dependent on the power control interference ratio (PCIR) ρ, the number of diversity paths identified by the receiver M, and the outage probability of the system. Simulation results are provided to validate the theoretical deductions. We conclude that the total effective channel capacity will be maximized as long as M4, and ρ0.5 for a proper value of .

In this paper, we explicitly construct a large class of symmetric Boolean functions on 2k variables with algebraic immunity not less than d, where integer k is given arbitrarily and d is a given suffix of k in binary representation. If let d = k, our constructed functions achieve the maximum algebraic immunity. Remarkably, 2⌊ log2k ⌋ + 2 symmetric Boolean functions on 2k variables with maximum algebraic immunity are constructed, which are much more than the previous constructions. Based on our construction, a lower bound of symmetric Boolean functions with algebraic immunity not less than d is derived, which is 2⌊ log2d ⌋ + 2(k-d+1). As far as we know, this is the first lower bound of this kind.

For the performance deficiency of the pilot symbol aided channel estimation in orthogonal frequency division multiplexing (OFDM) systems, the wavelets network interpolation channel estimator is proposed. By contrast with conventional methods, wavelets network interpolation channel estimator can guarantee the high transmission rate and lower Bit error rates (BER). Computer simulation results demonstrate that the proposed channel estimation method exhibit an improved performance compared to the conventional linear channel estimation methods and is robust to fading rate, especially in fast fading channels.

This paper investigates the resource allocation problem for the downlink of non-orthogonal multiple access (NOMA) networks. A novel resource allocation method is proposed to deal with the problem of maximizing the system capacity while taking into account user fairness. Since the optimization problem is nonconvex and intractable, we adopt the idea of step-by-step optimization, decomposing it into user pairing, subchannel and power allocation subproblems. First, all users are paired according to their different channel gains. Then, the subchannel allocation is executed by the proposed subchannel selection algorithm (SSA) based on channel priority. Once the subchannel allocation is fixed, to further improve the system capacity, the subchannel power allocation is implemented by the successive convex approximation (SCA) approach where the nonconvex optimization problem is transformed into the approximated convex optimization problem in each iteration. To ensure user fairness, the upper and lower bounds of the power allocation coefficients are derived and combined by introducing the tuning coefficients. The power allocation coefficients are dynamically adjustable by adjusting the tuning coefficients, thus the diversified quality of service (QoS) requirements can be satisfied. Finally, simulation results demonstrate the superiority of the proposed method over the existing methods in terms of system performance, furthermore, a good tradeoff between the system capacity and user fairness can be achieved.

Traditional face swapping technologies require that the faces of source images and target images have similar pose and appearance (usually frontal). For overcoming this limit in applications this paper presents a pose-free face swapping method based on personalized 3D face modeling. By using a deformable 3D shape morphable model, a photo-realistic 3D face is reconstructed from a single frontal view image. With the aid of the generated 3D face, a virtual source image of the person with the same pose as the target face can be rendered, which is used as a source image for face swapping. To solve the problem of illumination difference between the target face and the source face, a color transfer merging method is proposed. It outperforms the original color transfer method in dealing with the illumination gap problem. An experiment shows that the proposed face reconstruction method is fast and efficient. In addition, we have conducted experiments of face swapping in a variety of scenarios such as children's story book, role play, and face de-identification stripping facial information used for identification, and promising results have been obtained.

Ad hoc networks are becoming an interesting research area, as they inherently support unique network applications for the wireless communications in a rugged environment, which requires rapid deployment and is difficult to be provided by an infrastructure network. Many issues need to be addressed for the ad hoc networks. In this paper, we propose an efficient distributed coordination function on the media access control protocol to enhance the power conservation of mobile hosts by using a power control algorithm and the network throughput of an ad hoc network by using an algorithm for simultaneous frame transmissions. Extensive simulation is studied to evaluate the improvement of the proposed method. The results of the simulation exhibit significant improvement to the standard access control protocol. With slight improvement of network throughput, up to 85% of the consumed energy was able to be saved in compared to the standard protocol and up to 7 times of the energy efficiency was enhanced with the proposed method.

With the development of network technology, next-generation networks must satisfy many new requirements for network functions and performance. The processing of overlong packet fields is one of the requirements and is also the basis for ID-based routing and content lookup, and packet field addition/deletion mechanisms. The current SDN switches do not provide good support for the processing of overlong fields. In this paper, we propose a series of optimization mechanisms for protocol-oblivious instructions, in which we address the problem of insufficient support for overlong data in existing SDN switches by extending the bit width of instructions and accelerating them using SIMD instruction sets. We also provide an intermediate representation of the protocol-oblivious instruction set to improve the efficiency of storing and reading instruction blocks, and further reduce the execution time of instruction blocks by preprocessing them. The experiments show that our approach improves the performance of overlong data processing by 56%. For instructions involving packet field addition and deletion, the improvement in performance reaches 455%. In normal forwarding scenarios, our solution reduces the packet forwarding latency by around 30%.

In this paper, a scramble phase assisting weighted-type fractional Fourier transform (SPA-WFRFT) based system is proposed to guarantee the communication's security. The original transmitting signal is divided into two parts. The first part is modulated by WFRFT and subsequently makes up the constellation beguiling. The other part is used to generate the scramble phase and also to assist in the encryption of the WFRFT modulated signal dynamically. The novel constellation optimal model is built and solved through the genetic algorithm (GA) for the constellation beguiling. And the double pseudo scheme is implemented for the scramble phase generation. Theoretical analyses show that excellent security performances and high spectral efficiency can be attained. Final simulations are carried out to evaluate the performances of the SPA-WFRFT based system, and demonstrate that the proposed system can effectively degrade the unauthorized receivers' bit error rate (BER) performance while maintaining its own communication quality.

Survivable virtual network embedding (SVNE) is one of major challenges of network virtualization. In order to improve the utilization rate of the substrate network (SN) resources with virtual network (VN) topology connectivity guarantee under link failure in SN, we first establishes an Integer Linear Programming (ILP) model for that under SN supports path splitting. Then we designs a novel survivable VN topology protection method based on particle swarm optimization (VNE-PSO), which redefines the parameters and related operations of particles with the embedding overhead as the fitness function. Simulation results show that the solution significantly improves the long-term average revenue of the SN, the acceptance rate of VN requests, and reduces the embedding time compared with the existing research results.

Co-channel interference is a major deteriorating factor limiting the capacity of mobile communication systems. To mitigate the effect of the interference, a kind of nonlinear interference canceller named trellis-coded co-channel interference canceller (TCC) has been proposed. In TCC the trellis-coded modulation (TCM) is introduced to both the desired signal and the interference signal in order to enhance the cancelling performance. In this paper, the bit error rate (BER) performance of TCC in static channel is theoretically evaluated for the first time. An equivalent TCM (E-TCM) model is firstly established, and a BER asymptotic estimate (AE) and a BER upper bound (UB) of TCC are then evaluated respectively by analyzing E-TCM. In the evaluation of AE, the BER performance is calculated as a function of phase difference between the desired signal and the interference signal (φ), subsequently the average BER performance over φ can be evaluated. The UB of BER is calculated using a transfer function based on the matrix representation. This paper also demonstrates that AE gives higher accuracy and less calculation complexity than UB. Performance comparisons reveal the consistency of these theoretical results with that of computer simulations.

A method to construct Boolean functions with maximum algebraic immunity have been proposed in . Based on that method, we propose a different method to construct Boolean functions on even variables with maximum algebraic immunity in this letter. By counting on our construction, a lower bound of the number of such Boolean functions is derived, which is the best among all the existing lower bounds.

Elliptic curve cryptography (ECC), one of the asymmetric cryptography, is widely used in practical security applications, especially in the Internet of Things (IoT) applications. This paper presents a low-power reconfigurable architecture for ECC, which is capable of resisting simple power analysis attacks (SPA) and can be configured to support all of point operations and modular operations on 160/192/224/256-bit field orders over GF(p). Point multiplication (PM) is the most complex and time-consuming operation of ECC, while modular multiplication (MM) and modular division (MD) have high computational complexity among modular operations. For decreasing power dissipation and increasing reconfigurable capability, a Reconfigurable Modular Multiplication Algorithm and Reconfigurable Modular Division Algorithm are proposed, and MM and MD are implemented by two adder units. Combining with the optimization of operation scheduling of PM, on 55 nm CMOS ASIC platform, the proposed architecture takes 0.96, 1.37, 1.87, 2.44 ms and consumes 8.29, 11.86, 16.20, 21.13 uJ to perform one PM on 160-bit, 192-bit, 224-bit, 256-bit field orders. It occupies 56.03 k gate area and has a power of 8.66 mW. The implementation results demonstrate that the proposed architecture outperforms the other contemporary designs reported in the literature in terms of area and configurability.

To overcome the false lock or detection missing problems caused by the multiple peaks of the auto-correlation function (ACF) of Binary Offset Carrier (BOC) modulated signal, an acquisition algorithm based on unit correlation for BOC(n,n) signal is proposed in this paper. The local BOC signal is separated into two unit signals, an odd one and an even one. Then a reconstruction of the unit correlation functions between the unit signals and the received BOC signal is performed and M sections of reconstructed correlation function are accumulated according to the non-coherent method, so that this novel acquisition algorithm can not only eliminate the multiple secondary peaks, but also retain the advantage of the narrow correlation main peak. Simulation results show that the acquisition sensitivity of the proposed algorithm is increased 3dBHz compared with the ASPeCT method, and the computation cost is only 41.46% of the ASPeCT method when M=2.

Multi-rate capabilities are supported by the physical layers of most 802.11 devices. To enhance the network throughput of MANETs, transfer rate adaptation schemes at MAC layer should employ the multi-rate capability at physical and the information of previous transmissions provided by MAC and physical layers. In this paper, we propose a transfer rate adaptation scheme plus back-to-back frame transmissions, and fragmentation at MAC layer, named TRAF. TRAF adopts a bi-direction-based approach with an extended option to select an appropriate rate for frame transmission under fast changing channel conditions. Consecutive back-to-back frame transmissions to fully utilize good channel quality during a coherent time interval and fragmentation algorithm to maintain high throughput under worse channel conditions are recommended in TRAF. Extensive simulation is experimented to evaluate the performance of TRAF. Regarding simulation results, frame delivery ratio, network throughput, and fairness of TRAF are significantly improved by comparing to that of fix rate, ARF, RBAR, OAR, and AAR protocols.

By close analogy of annealing for solids, we devise a new algorithm, called APS, for the time evolution of both the state and the synapses of the Hopfield's neural network. Through constrainedly random perturbation of the synapses of the network, the evolution of the state will ignore the tremendous number of small minima and reach a good minimum. The synapses resemble the microstructure of a network. This new algorithm anneals the microstructure of the network through a thermal controlled process. And the algorithm allows us to obtain a good minimum of the Hopfield's model efficiently. We show the potential of this approach for optimization problems by applying it to the will-known traveling salesman problem. The performance of this new algorithm has been supported by many computer simulations.

High frame rate and ultra-low delay are the most essential requirements for building excellent human-machine-interaction systems. As a state-of-the-art local keypoint detection and feature extraction algorithm, A-KAZE shows high accuracy and robustness. Nonlinear scale space is one of the most important modules in A-KAZE, but it not only has at least one frame delay and but also is not hardware friendly. This paper proposes a hardware oriented nonlinear scale space for high frame rate and ultra-low delay A-KAZE matching system. In the proposed matching system, one part of nonlinear scale space is temporally forward and calculated in the previous frame (proposal #1), so that the processing delay is reduced to be less than 1 ms. To improve the matching accuracy affected by proposal #1, pre-adjustment of nonlinear scale (proposal #2) is proposed. Previous two frames are used to do motion estimation to predict the motion vector between previous frame and current frame. For further improvement of matching accuracy, pixel-level pre-adjustment (proposal #3) is proposed. The pre-adjustment changes from block-level to pixel-level, each pixel is assigned an unique motion vector. Experimental results prove that the proposed matching system shows average matching accuracy higher than 95% which is 5.88% higher than the existing high frame rate and ultra-low delay matching system. As for hardware performance, the proposed matching system processes VGA videos (640×480 pixels/frame) at the speed of 784 frame/second (fps) with a delay of 0.978 ms/frame.

In this paper, we present CB-Power, a hierarchical power analysis and characterization environment of cell-based CMOS circuits. The environment includes two parts, a cell characterization system for timing, input capacitance as well as power and a cell-based power estimation system. The characterization system can characterize basic, complex and transmission gates. During the characterization, input slew rate, output loading, capacitive feedthrough effect and the logic state dependence of nodes in a cell are all taken into account. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power and dynamic power. With the characterization data, a cell-based power estimator (CBPE) embedded in Verilog-XL is used for estimating the power consumption of the gates in a circuit. CBPE is also a hierarchical power estimator. Macrocells such as flip-flops and adders are partitioned into primitive gates during power estimation. Experimental results on a set of MCNC benchmark circuits show that the power estimation based on our power modeling and characterization provides within 6% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.

As the function of a system getting more complex, IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.