This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13 µm, 1.2 V CMOS process. Experiments show that when the clock frequency is 32 MHz, the power consumption of the proposed decoder is 38.4 mW, the energy efficiency is 53.3 pJ/bit/ite and the core area is 1.8 mm2.

Vertical stacking is a novel technique for creating nonblocking (crosstalk-free) optical multistage interconnection networks (MINs). In this paper, we propose a new class of optical MINs, the vertically stacked Benes (VSB) networks, for crosstalk-free realization of permutations in a single pass. An NN VSB network requires at most O(Nlog N) switching elements, which is the same as the Benes network, and much lower overall hardware cost than that of the existing optical MINs built on the combination of horizontal expansion and vertical stacking of banyan networks, to provide the same crosstalk-free permutation capability. Furthermore, the structure of VSB networks provides a more flexible way for constructing optical MINs because they give more choices in terms of the number of stages used in an optical MIN. We also present efficient algorithms to realize crosstalk-free permutations in an NN VSB network in time O(Nlog N), which matches the same bound as required by the reported schemes.