This paper presents a new cycle time synchronization method to transmit isochronous multimedia data by real time in IEEE 1394 over a UWB (ultra wide-band) network. The 1394 TA recommended two methods for the cycle time synchronization. The first method must use two consecutive beacon signals to calculate a drift correction, while the second one eliminates this dependency with minor algorithm changes. As experimental results, the second method achieves 21% performance improvement over the first one. The receipt of two consecutive beacons every time is hard due to the noise in a wireless channel. In addition, this paper provides the procedure of cycle time synchronization, as well as the transaction between 1394 protocol adaptation layer and IEEE 802.15.3 media access layer. The proposed synchronization technique will contribute to transfer isochronous data at IEEE 1394 over UWB audio/visual appliances such as camcorder, HDTV, etc.

When a store sells items to customers, the store wishes to decide the prices of items to maximize its profit. Intuitively, if the store sells the items with low (resp. high) prices, the customers buy more (resp. less) items, which provides less profit to the store. So it would be hard for the store to decide the prices of items. Assume that the store has a set V of n items and there is a set E of m customers who wish to buy the items, and also assume that each item i ∈ V has the production cost di and each customer ej ∈ E has the valuation vj on the bundle ej ⊆ V of items. When the store sells an item i ∈ V at the price ri, the profit for the item i is pi=ri-di. The goal of the store is to decide the price of each item to maximize its total profit. We refer to this maximization problem as the item pricing problem. In most of the previous works, the item pricing problem was considered under the assumption that pi ≥ 0 for each i ∈ V, however, Balcan, et al. [In Proc. of WINE, LNCS 4858, 2007] introduced the notion of "loss-leader," and showed that the seller can get more total profit in the case that pi < 0 is allowed than in the case that pi < 0 is not allowed. In this paper, we consider the line highway problem (in which each customer is interested in an interval on the line of the items) and the cycle highway problem (in which each customer is interested in an interval on the cycle of the items), and show approximation algorithms for the line highway problem and the cycle highway problem in which the smallest valuation is s and the largest valuation is (this is called an [s,]-valuation setting) or all valuations are identical (this is called a single valuation setting).

Multi-source broadcasting is one of the information dissemination problems on communication networks such that some units disseminate distinct messages to all other units. In this paper, we study multi-source broadcasting on the de Bruijn and Kautz digraphs which are the models of interconnection networks. In [8] and [12], a cycle-rooted tree which has a large root-cycle is constructed by composition of isomorphic factors, and the multi-source broadcasting is executed on the cycle-rooted tree. On the other side, we execute multi-source broadcasting on each isomorphic factors at the same time. We present a method for multi-source broadcasting using isomorphic cycle-rooted trees which factorize these digraphs, and investigate its efficiency.

The fuzzy controller based on cycle-to-cycle control with output value adjustment factors (OAF) was developed for restoring gait of paralyzed subjects by using functional electrical stimulation (FES). Results of maximum knee flexion and extension controls with neurologically intact subjects suggested that the OAFs would be effective in reaching the target within small number of cycles and in reducing the error after reaching the target. Oscillating responses between cycles were also suppressed. The fuzzy controller was expected to be examined to optimize the OAFs with more subjects including paralyzed patients for clinical application.

A wide range, low jitter Duty Cycle Corrector (DCC) based on continuous-time integrator is proposed. It introduces little added jitter in the sampling edge, which make it good candidate for pipelined ADC application. The circuit is implemented in CMOS 0.35 µm 2P4M Mixed Signal process. The experimental results show the circuit can work for a wide frequency range from 500 kHz to 280 MHz, with a correction error within 50%1% under 200 MHz, and the acceptable duty cycle can be as wide as 1-99% for low frequency inputs.

Microarray technology has been applied to various biological and medical research fields. A preliminary step to extract any information from a microarray data set is to identify differentially expressed genes between microarray data. The identification of the differentially expressed genes and their commonly associated GO terms allows us to find stimulation-dependent or disease-related genes and biological events, etc. However, the identification of these deregulated GO terms by general approaches including gene set enrichment analysis (GSEA) does not necessarily provide us with overrepresented GO terms in specific data among a microarray data set (i.e., data-specific GO terms). In this paper, we propose a statistical method to correctly identify the data-specific GO terms, and estimate its availability by simulation using an actual microarray data set.

Let u and v be any two distinct vertices of an undirected graph G, which is k-connected. For 1 w k, a w-container C(u, v) of a k-connected graph G is a set of w-disjoint paths joining u and v. A w-container C(u, v) of G is a w *-container if it contains all the vertices of G. A graph G is w *-connected if there exists a w *-container between any two distinct vertices. Let κ(G) be the connectivity of G. A graph G is super spanning connected if G is i *-connected for 1 i κ(G). In this paper, we prove that the n-dimensional burnt pancake graph Bn is super spanning connected if and only if n ≠ 2.

In this paper, performance of a novel interference cancellation technique for the single user detection in a direct-sequence code-division multiple access (DS-CDMA) system has been investigated. This new algorithm is based on the Cycle-and-Add property of PN (Pseudorandom Noise) sequences and can be applied for both synchronous and asynchronous systems. The proposed strategy provides a simple method that can delete interference signals one by one in spite of the power levels of interferences. Therefore, it is possible to overcome the near-far problem (NFP) in a successive manner without using transmit power control (TPC) techniques. The validity of the proposed procedure is corroborated by computer simulations in additive white Gaussian noise (AWGN) and frequency-nonselective fading channels. Performance results indicate that the proposed receiver outperforms the conventional receiver and, in many cases, it does so with a considerable gain.

To be adaptive to the bursty traffic of the wireless personal area network (WPAN), a superframe structure adjustment algorithm of IEEE 802.15.4 is proposed. According to the channel utilization ratio which is an index of the traffic load, the algorithm adjusts the duty cycle of the superframe automatically. The simulation results show that the algorithm is adaptive to the traffic variations effectively and saves much more energy not only for the end devices but also for the PAN coordinator. Moreover, the algorithm results in better performance on the lower delay and lower packet dropping rate.

The weakness of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which lead to limited throughput. In this letter in order to construct efficient architecture, we target on IEEE 802.16e LDPC encoders. Over the standard H matrices with Circulant Permutation Matrices, we propose semi-parallel architecture by using cyclic right shift registers and exclusive-OR instead of complex Matrix Vector Multipliers. Proposed efficient encoder for IEEE 802.16e LDPC satisfies compact size and high throughput.

In high-precision positioning systems, the limit cycles induced by friction effects result in a significant reduction in the positioning performance; particularly when the servo system utilizes a high gain controller. Accordingly, the current study presents a compensation scheme consisting of a dead-zone function and an integral term to limit the equivalent gain of unspecified controllers to the stable range. The proposed compensation scheme not only ensures that the feedback loop system remains stable, but also provides a simple and effective mechanism for preventing the users from inadvertently setting control gains which degrade the positioning performance of the system. The simulation results confirm the ability of the gain limit compensation scheme to suppress the effects of limit cycles and therefore demonstrate its feasibility for practical applications.

This paper proposes methods to improve soft-input and soft-output decoding performance of BCH codes by sum-product algorithm (SPA). A method to remove cycles of length four (RmFC) in the Tanner graph has been proposed. However, the RmFC can not realize good decoding performance for BCH codes which have more than one error correcting capability. To overcome this problem, this paper proposes two methods. One is to use a parity check matrix of the echelon canonical form as the starting check matrix of RmFC. The other is to use a parity check matrix that is concatenation (ConC) of multiple parity check matrices. For BCH(31,11,11) code, SPA with ConC realizes Eb/No 3.7 dB better at bit error rate 10-5 than the original SPA, and 3.1 dB better than the SPA with only RmFC.

Functional Electrical Stimulation (FES) can be effective in assisting or restoring paralyzed motor functions. The purpose of this study is to examine experimentally the fuzzy controller based on cycle-to-cycle control for FES-induced gait. A basic experimental test was performed on controlling maximum knee extension angle with normal subjects. In most of control trials, the joint angle was controlled well compensating changes in muscle responses to electrical stimulation. The results show that the fuzzy controller would be practical in clinical applications of gait control by FES. An automatic parameter tuning would be required practically for quick responses in reaching the target and in compensating the change in muscle responses without causing oscillating responses.

Longest path problem is a problem for finding a longest path in a given graph. While the graph classes in which the Hamiltonian path problem can be solved efficiently are widely investigated, there are few known graph classes such that the longest path problem can be solved efficiently. Polynomial time algorithms for finding a longest cycle and a longest path in a Ptolemaic graph are proposed. Ptolemaic graphs are the graphs that satisfy the Ptolemy inequality, and they are the intersection of chordal graphs and distance-hereditary graphs. The algorithms use the dynamic programming technique on a laminar structure of cliques, which is a recent characterization of Ptolemaic graphs.

A new algorithm is proposed to reduce the area of a pipelined circuit using a combination of multi-clock cycle paths, clock scheduling and delay balancing. The algorithm analyzes the circuit and replaces intermediate registers with delay elements under the condition that the circuit works correctly at given target clock-period range with the smaller area. Experiments with pipelined multipliers verify that the proposed algorithm can reduce the area of a pipelined circuit without degrading performance.

This letter describes a digitally controlled duty cycle corrector (DCC) with 1 ps resolution. A new half period delay line (HPDL) control scheme using a delay locked loop (DLL) is proposed. The DCC has an output duty error less than 0.5% for 25% input duty error and operates correctly from 200 MHz to 800 MHz in a 0.18 µm CMOS technology.

In this paper, we propose one low-computation cycle and power-efficient recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architecture adopting a hybrid of input strength reduction, the Chebyshev polynomial, and register-splitting schemes. Comparing with the existing recursive DFT/IDFT architectures, the proposed recursive architecture achieves a reduction in computation-cycle by half. Appling this novel low-computation cycle architecture, we could double the throughput rate and the channel density without increasing the operating frequency for the dual tone multi-frequency (DTMF) detector in the high channel density voice over packet (VoP) application. From the chip implementation results, the proposed architecture is capable of processing over 128 channels and each channel consumes 9.77 µW under 1.2 V@20 MHz in TSMC 0.13 1P8M CMOS process. The proposed VLSI implementation shows the power-efficient advantage by the low-computation cycle architecture.

An 8.8-GS/s 6-bit CMOS analog-to-digital converter (ADC) chip was implemented by time-interleaving eight 1.1-GS/s 6-bit flash ADCs with a 0.18-µm CMOS process. Eight uniformly-spaced 1.1 GHz clocks with 50% duty cycle for the eight flash ADCs were generated by a clock generator, which consists of a phase-locked-loop, digital phase adjusters and digital duty cycle correctors. The input bandwidth of ADC with the ENOB larger than 5.0 bits was measured to be 1.2 GHz. The chip area and power consumption were 2.24 mm2 and 1.6 W, respectively.

We propose a novel paging scheme with a variable paging interval for low power consumption and/or short paging delay. The proposed scheme is based on the fact that packet arrivals during a session follow the characteristics of self-similar process for Http service, while session arrival statistics can be modeled as the Poisson process. The adjustment of paging period provides a useful solution for efficient paging to the UE in the dormant state on packet-switched cellular networks, even though the paging performance is strongly dependent on the traffic arrival model.

A second order charge pump (SOCP) scheme is proposed in this letter. Compared with the conventional single charge pump, the second order charge pump does not suffer phase errors caused by the output voltage dependent current mismatches. Also, the second order charge pump can be implemented in a mixed-mode type, enabling the fast lock and the various operation modes simultaneously. The proposed SOCP has been adopted into the duty cycle corrector (DCC) loops of DDR2 DRAM, and shows a much widened correction range owing to the removal of the parasitic effects.