This letter describes consecutive zero and one bits detection circuits designed for a 1.25 Gbit/s burst mode laser driver realized in a SiGe 0.35 µm BiCMOS technology with 3.3 V power supply. The architecture is based on a frequency divider and a delay line counting per four consecutive zero or one bits. The detector was designed with high-speed split-output stage flip-flops modified to have a reset input. Experimental results validate the design of the detector.

A mechanical phase shifter is designed for beam scanning in co-phase fed single-layer slotted waveguide arrays. The multiple-way power divider in this array consists of a series of π-junctions with one guide wavelength spacing in a feed waveguide. The movable narrow walls placed between the π-junctions perturb the guide wavelength as well as the phase of output ports. Method of Moment (MoM) analysis for one unit consisting of one movable plate and two junctions is conducted to estimate the available phase shift as well as the degradation of reflection. A phase shift of 86 degrees is predicted between two π-junctions under the condition of reflection below -20 dB; experiments at 4 GHz confirmed the design. The beam scanning capability of the arrays is also surveyed and the beam-scanning of about 10 degrees is predicted.

A CMOS voltage-mode divider, which can operate for low supply voltage and low power dissipation, is presented in this paper. The proposed voltage-mode divider can be used to realize a pseudo-exponential function generator. The experimental results of the proposed voltage-mode divider show that, under the supply voltage VDD=2.5 V, the linearity error is less than 1.18% and the power consumption is only 102 µW. Also the proposed pseudo-exponential function generator exhibits a 15 dB output dynamic range and the linear error is less than1.54%. Both the proposed circuits have been fabricated in a 0.5 µm N-well CMOS 2P2M process. The proposed circuits are expected to be useful in analog signal processing applications.

This paper describes a three-port power divider with compensation networks for non-ideal isolation resistor. The compensation networks consist of two pairs of transmission lines and cancel out the parasitic reactance of the non-ideal isolation resistor. The design equations to provide perfect return loss and isolation at a center frequency are presented. The availability of the proposed power divider has been verified by the comparison between calculated and experimental results in the Ku-band.

The authors propose a novel 3-way power divider named a planar cross-junction, which is used as the center feed for single-layer slotted waveguide arrays. A feeding waveguide consisting of a cascade connection of these dividers is placed at the middle of radiating waveguide in a single layer. The length of radiating waveguides is halved; the long line effect in traveling wave operation is halved and bandwidth is widened. One divider as a unit is designed by Galerkin's method of moments to suppress the reflection and to control the amplitude and the phase of the divided power into two radiating waveguides on both sides of a feed one. Two types of the cross-junction with a different divided power ratio are designed and tested by experiments in 4 GHz band. The mutual coupling effects between two adjacent cross-junctions as cascaded in a feeding waveguide of the array are predicted to be small enough; units designed here are directly applicable for a multiple-way power divider.

This paper describes a simple design of a broad-band four-way power divider with 45-degree phase differences between output ports. In the first stage of our work, we present a new broad-band 90-degree power divider. The phase error of the power divider here is less than one-tenth of the conventional 90-degree branch-line hybrid. Next, an experimental UHF-band four-way power divider using a broad-band 90-degree power divider and two broad-band 45-degree power dividers is presented. Over the frequency range from 0.86 to 1.06 GHz, the experimental four-way power divider exhibits power splits of -6.420.25 dB, return losses of greater than 15 dB, errors in the desired relative-phase difference between output ports of less than 1 degree, and isolation between output ports of greater than 15 dB. This divider is useful for realizing low distortion and high efficiency amplifiers without the need for an isolator.

This paper describes an electromagnetically coupled microstrip divider that provides high output port isolation and DC cutting. The device consists of a parasitic resonator placed above microstrip patch resonators, achieving tight coupling for both input and output ports. FDTD simulation and measurements reveal that the device has a high isolation between output ports. Equal and unequal 2-way and 3-way power dividers are presented in this paper.

In this paper, a novel three-port antenna structure, named 180 antenna hybrid, is proposed and demonstrated. This structure is composed of a Wilkinson power divider with the isolation resistor replaced by an aperture-coupled patch antenna. The equivalent series impedance of the antenna can be adjusted to the required one by properly choosing the dimensions of the patch and the coupling aperture. When a signal is fed to the balanced port of this antenna hybrid, the power is equally split, with equal phases, to the two unbalanced ports. No power is radiated out from the antenna. In the other hand, a signal received from the antenna will be split with equal power but 180 phase difference to the two unbalanced ports. The balanced port is an isolation port. The measurement results showed good agreement with the characteristics to be designed. Three applications of this 180 antenna hybrid are introduced, that is, a balanced mixer, an active transmitting antenna, and a dual-radiation-mode antenna array. The balanced mixer was constructed with diodes directly mounted on the two unbalanced ports of the antenna hybrid. The LO signal is fed from the balanced port and RF signal is received from the antenna. The active transmitting antenna was implemented with feedback configuration. The route from one of the unbalanced port to the balanced port of the antenna hybrid was used as the feedback path. A locking signal may be injected from the other unbalanced port. Finally, through a three-quarter-wavelength microstrip line, the balanced port of the antenna hybrid was connected to another aperture-coupled patch antenna to form a dual-radiation-mode antenna array. The in-phase and out-of-phase radiation patterns of this two-element array can be obtained from two unbalanced ports of the antenna hybrid, respectively.

In the phase locked loop (PLL) frequency synthesizer which is used in a higher frequency region, the prescaler method is employed in order to increase the operating frequency of the programmable divider. However, since the fixed divider whose division ratio is same as the prescaler is installed at the following stage of the reference divider, the reference frequency is decreased and the performance of the PLL frequency synthesizer is degraded. The prescaler PLL frequency synthesizer using multi-programmable divider is one of the counter measures answering the request. In this paper we propose the reduction of the number of programmable dividers by using the (N+1/2) programmable divider. The effectiveness of the proposed method is confirmed by experimental results.

49-GHz operation for a state-of-the-art static frequency divider using FETs is achieved with high-performance 0.1-µm-gate InAlAs/InGaAs/InP HEMTs and high-speed double-layer interconnections with a thick low-permittivity BCB inter-layer dielectric film. An experiment shows that the propagation delay for the upper-layer line in the double-layer interconnections is less than half of that for the conventional single-layer interconnections directly on InP-substrate. The frequency divider with the double-layer interconnections is about 20% faster than the conventional one with the single-layer interconnections. A delay time analysis reveals that this speed increase is due to the decrease in interconnection propagation delay.

We have developed a fabrication technique for high-performance high-thermal-stability InP/InGaAs heterojunction bipolar transistors (HBTs) for use in 40-Gb/s ICs. The HBT's T-shaped emitter electrode structure simplifies the fabrication process and enables high controllability of spacing between the emitter and the base electrodes. A highly-C-doped base, grown by gas-source MBE, and a new Pt-based metal system results in a low base resistance. An InP subcollector suppresses thermal runaway of HBTs at high collector current better than a conventional InGaAs subcollector does. Using these techniques, we fabricated a very-high-performance HBT with an extremely high cutoff frequency fT of 235 GHz. The RF measurements show that the collector current at the peak cutoff frequency is inversely proportional to collector thickness. We also fabricated a static 1/2 frequency divider, that can be used for 40-Gb/s optical transmission systems, operating up to 44 GHz. This divider confirmed that the developed HBT is applicable to 40-Gb/s optical transmission ICs.

This paper describes a new floating-point divider (FDIV), in which the key features of redundant binary circuits and an asynchronous clock scheme reduce the delay time and area penalty. The redundant binary representation of +1 = (1, 0), 0 = (0, 0), -1 = (0,1) is applied to the all mantissa division circuits. The simple and unified representation reduces circuit delay for the quotient determination. Additionally, the local clock generator circuit for the asynchronous clock scheme eliminates clock margin overhead. The generator circuit guarantees the worst delay-time operation by the feedback loop of the replica delay paths via a C-element. The internal iterative operation by the asynchronous scheme and the modified redundant-binary addition/subtraction circuit keep the area small. The architecture design avoids extra calculation time for the post processes, whose main role is to produce the floating-point status flags. The FDIV core using proposed technologies operates at 42. 1 ns with 0.35 µm CMOS technology and triple metal interconnections. The small core of 13.5 k transistors is laid-out in a 730µm 910 µm area.

In order to develop high-speed ICs, it is important to clarify the relationship between circuit speed and device parameters. An analytical expression for circuit performance is effective for this purpose. This paper describes an analytical toggle frequency expression for Source-Coupled FET Logic (SCFL) frequency dividers. The proposed equation is expressed as the sum of the product of sensitivity coefficients of FET parameters and time constants which are extracted through a small signal transfer function analysis. These sensitivity coefficients are extracted using SPICE simulations. The equation is a simple formula with only five coefficients, which is much smaller than conventional sensitivity analyses. Furthermore, the accuracy of the proposed equation is improved compared to an analytical method based on the small signal transfer function which we previously proposed. The equation can be easily extended to consider interconnection delay time. The calculated maximum toggle frequencies using the equation show good agreement with SPICE simulations and experimental results for a wide gate-length variation range of 0. 12-µm to 0. 24-µm GaAs MESFETs. By re-extraction of another set of sensitivity coefficients, the proposed equation can be widely applied to shorter gate-length GaAs MESFETs and other FET devices such as HEMT devices. The expression clearly shows the relationship between the circuit performance and intrinsic FET parameters. According to the equation, the key parameters for high-speed circuit operation are high transconductance with a low drain conductance, and a low gate-drain capacitance. The equation can be used as a criterion for the optimization of the FET structure to realize high speed circuit performance.

A high power amplifier module has been developed for large cell base station in digital cordless system. For PHS application, this module exhibited Pout of 38 dBm with low ACP of -72 dBc (at 600 kHz offset point) and a power gain of 33 dB at a supply voltage of 9 V and a frequency range of 1890-1923 MHz. In order to realize this ultra low distortion performance, power FETs have been designed as considering high breakdown voltage and thermal stability. Power divider/combiner circuits, which have the advantages of low transmission loss and a function of controlling second harmonic, have been introduced. Moreover, a novel module package with features of low cost and good processing precision has been proposed.

The authors propose a novel waveguide two-way power divider, named as τ-junction, in a feed waveguide of a single-layer slotted waveguide array antenna. This junction occupies only a small space and is placed in the middle of a cascade of several power dividers. It suppresses the long line effect and widens the bandwidth of the feed waveguide. The junction has two inductive walls; one is for suppressing the reflection and the other is for controlling the ratio of divided power to the two output ports. Analysis using Galerkin's method of moments is verified by experiments of a 4 GHz-band model. We install the junctions in a 12 GHz-band single-layer slotted waveguide array. The gain reduction at the band-edge is suppressed.

This paper proposes a set of three IF-band MMICs for high-speed wireless communication systems. The first of the circuits in this chip set is an MMIC logarithmic limiting receiver amplifier. This amplifier utilizes the self-phase distortion compensation technique, combining a common-source FET and a common-drain FET, to reduce phase distortion. The limiting characteristics were gain of more than 65 dB, 2. 2-dBm saturated output power and phase deviation of less than 5. A logarithmic accuracy of 2 dB and RSSI change coefficient of more than 11 mV/dB were also achieved. Typical power consumption was less than 0. 58 W with the supply voltages of +3 V and -2 V. The second of the fabricated circuits is an MMIC transmitter amplifier with more than 24-dB gain at 140 MHz. And the third of the fabricated circuits is an MMIC 90 signal divider and combiner. This MMIC combines a set of amplifiers with a set of dividers having a constant phase difference of 90. Thus the isolation between the transmission port and the reception port is obtained. The chip size is less than 1/100 that of a commercial 140-MHz-band 90 coupler. At the frequency of 140 MHz, the mean transmission loss is about 2. 1 dB for the divider part and 3. 0 dB for the combiner part. Furthermore, in the frequency range of 130 MHz to 150 MHz, signal leakage from the transmission port to the reception port is suppressed by more than 24 dB.

Investigated is a guided-wave device for dividing optical power into three equal parts. The device fundamentally consists of a three-waveguide tapered-velocity coupler which is designed to operate under the adiabatic condition. Field distributions of the local normal modes along the coupler explain basic principles of the device. Its performance is confirmed through numerical simulations by means of finite difference beam propagation method.

A small-sized three-stage GaAs power module has been developed for portable digital radios using M-16QAM modulation. This module has exhibited typical P1dB of 10 W with PAE of 48% and a power gain of 35 dB at a low supply voltage of 6.5 V in 1.453-1.477 GHz band. The volume of the module is only 1.5 cc, which is one of the smallest value in 10 W class modules ever reported. In order to realize the reduced size and the high power performances simultaneously, the module has employed new power divider/combiner circuits with significant features of the reduced occupation area, the improved isolation properties and the function of second-harmonic control.

A high-speed silicon-on-insulator (SOI) of a 1/8 frequency divider and a 64-bit adder were realized using an optimized gate-overlapped LDD and a self-aligned titanium silicide (TiSi2) source-drain structure. The advantages of the delay time and power consumption were analyzed by circuit simulation. The maximum operation frequency of the SOI divider is 2.9 GHz at 3.3 V. The SOI divider operates about 1.6 times faster than the bulk-Si divider. The power consumption of the SOI divider at the maximum operating frequency is about 60% of that of the bulk divider. On the other hand, the speed of the SOI adder is 1.9 nsec at 3.3 V. The SOI adder speed is about 1.3 times faster than the bulk adder. The power consumption of the SOI adder is about 80% of that of the bulk divider. It was found that the high speed, low power features of the SOI divider were due to the pass transistor which had low junction capacitance and little substrate bias effects, in addition to the low wiring capacitance and low fanout capacitance compared to the bulk adder. As a result, it is suggested that SOI circuits using pass transistor have a potential for GHz level systems and it is expected they will be applied to handy communication systems and portable computers used in the multimedia era.

In this paper, in order to achieve the low power consumption of programmable divider in a PLL frequency synthesizer, we propose a new prescaler method for low power consumption. A fixed prescaler is inserted in front of the (N +1/2) programmable divider which is designed based on the new principle. The divider ratio in the loop does not vary at all even if such a prescaler is utilized. Then the permissible delay periods of a programmable divider can be extended to two times as long as the conventional method, and the low power consumption and low cost in a PLL frequency synthesizer have been achieved.