A new current-mode analog BiCMOS multiplier/divider circuit based on the translinear principle is presented. This circuit can be implemented by a standard 0.8µm BiCMOS process. The simulation results showed that the circuit realizes the high-speed and high-precision operation with a 3V supply.

A two-waveguide tapered velocity coupler is presented for a variable divider of optical beams. The coupler consists of one tapered slab waveguide in dimension and the other slab waveguide with a constant film thickness. It is assumed that the device is fabricated on a LiNbO3 substrate, with a push/pull external electric field parallel with the optic axis applied only in the film regions of the coupler. Various numerical simulations through the finite difference beam propagation analysis show that a wide range of dividing ratios from - 15 dB to 15 dB or more can be achieved with considerably small values of driving-voltage electrode-length product and that the dividing characteristics are stable over a wide range of frequencies.

The authors propose a waveguide π-junction with an inductive wall. Galerkin's method of moments is applied to analyze it and small reflection and desired power division ratio is realized. Good agreement between the calculated result and the measured one verifies the design of a unit π-junction. The characteristics of aπ-junction with a wall are almost the same as those of a conventional π-junction with a post. Important advantage of the new π-junction with a wall is that it can be manufactured in the die-cast process of the waveguide while a post in the conventional one must be attached in an additional process. A 16-way power divider consisting of 8 π-junctions is designed at 11.85 GHz and the characteristics are predicted.

A 0.1-µm gate-length GaAs MESFET technology is reported. A 48.3-GHz dynamic-frequency divider, and an amplifier with 20-dB gain and 17.5-GHz bandwidth are successfully fabricated by integrating over-100-GHz-cut-off frequency MESFETs using a new lightly-doped drain structure with a buried p-layer (BP-LDD) device structure.

This paper deals with an efficient radix-2 divider design theory that uses carry-propagation-free adders based on redundant binary{1, 0, 1} representation. In order to compute the division fast, we look ahead to the next step quotient-digit selection embedded in the current partial remainder calculation. The solution is a function of the four most significant digits of the current partial remainder, when scaling the divisor in the range [1, 9/8). In gate depth, this result is better than the higher radix-4 case without the look-ahead quotient-digit selection and the design is simple.

A Radial Line Slot Antenna (RLSA) is a planar antenna for DBS reception. It is a kind of slotted waveguide arrays. The conductor loss is so small that high efficiency is expected irrespective of the aperture diameter. On the other hand, since a RLSA utilizes the traveling waves, the frequency bandwidth is limited by the long line effect, particularly for a larger antenna. A new Wide-Band RLSA (WB-RLSA) is proposed which halves the waveguide length and widens the frequency bandwidth. This paper presents the design and experimental results of a model antenna. A gain of 33.7dBi is measured at the edge of 800MHz bandwidth and its high potential is demonstrated.

This paper describes IC-oriented high-performance AlGaAs/GaAs heterojunction bipolar transistors that were fabricated to demonstrate their great potential in applications to high-speed integrated circuits. A collector structure of ballistic collection transistors with a launcher (LBCTs) shortens the intrinsic delay time of the transistors. A novel and simple self-aligned fabrication process, which features an base-metal-overlaid structure (BMO), reduces emitter- and base-resistances and collector capacitance. The combination of the thin-collector LBCT layer structure and the BMO self-alignment technology raises the average value of cutoff frequency, fT, to 160 GHz with a standard deviation as small as 4.3 GHz. By modifying collector thickness and using Pt/Ti/Pt/Au as the base ohmic contact metal in BMO-LBCTs, the maximum oscillation frequency, fmax, reaches 148 GHz with a 114 GHz fT. A 2:1 multiplexer with retiming D-type flip-flops (DFFs) at input/output stages fabricated on a wafer with the thin-collector LBCT structure operates at 19 Gbit/s. A monolithic preamplifier fabricated on the same wafer has a transimpedance of 52 dBΩ with a 3-dB-down bandwidth of 18.5 GHz and a gain S21 OF 21 dB with a 3-dB-down bandwidth of 19 GHz. Finally, a 40 Gbit/s selector IC and a 50 GHz dynamic frequency divider that were successfully fabricated using the 148-GHz fmax technologies are described.

This paper deals with the theory and design method of an efficient radix-4 divider using carry-propagation-free adders based on redundant binary {-1,0,+1} representation. The usual method of normalizing the divisor in the range [1/2,1) eliminates the advantages of using a higher radix than two, bacause many digits of the partial remainder are required to select the quotient digits. In the radix-4 case, it is shown that it is possible to select the quotient digits to refer to only the four (in the usual normalizing method it is seven) most significant digits of the partial remainder, by scaling the divisor in the range [12/8,13/8). This leads to radix-4 dividers more effective than radix-2 ones. We use the hyperstring graph representation proposed in Ref.(18) for redundant binary adders.

We are presenting a high-speed MOS multiplier and divider, which is based on a redundant binary representation (using the digits 1, 0, 1), and their implementation in a 64-bit RISC microprocessor. The multiplier uses a redundant binary adaptation of the Booth algorithm and a redundant binary adder tree. We compared it to a multiplier using a two bit version of the Booth algorithm and a Wallace tree and found that the former multiplier is useful in VLSI because of its high-speed operation, small number of transistors, and good regularity. We also found that the divider performed by Newton's iteration using the multiplier is useful in VLSI. Implementing the multiplier and divider in a highly integrated 64-bit RISC microprocessor, we obtained a high-speed microprocessor.

A one-by-four static frequency divider using AlGaAs/GaAs heterojunction bipolar transistors (HBTs) was designed to operate at a bias condition that gave a maximum cutoff frequency fT and a maximum oscillation freqency fmax. The fT and fmax applied to the divider were 68 GHz and 56 GHz, respectively. As a result of the tests, the circuit operated up to 34.8 GHz at a power supply voltage of 9 V and power dissipation of 495 mW. A low minimum input signal power level of 0 dBm was also achieved.

A 1/2 frequency divider using resonant-tunneling hot electron transistors (RHETs) has been proposed and demonstrated. The circuit make the best use of negative differential conductance, a feature of RHETs, and contains one half transistors than used in conventional circuits. The RHETs were fabricated using self-aligned InGaAs RHETs and WSiN thin-film resistors on a single chip. The RHETs have an i-InGaAlAs/i-InGaAs collector barrier that improves the current gain at low collector-base voltages. Circuit operation was confirmed at 77 K.

The authors design a simple feed system for a planar slotted waveguide array. A waveguide π-junction with negligible reflection is cascaded to compose a multiple-way power divider. The frequency characteristics of the power divided to each port and the reflection at the feed point are discussed and high performances are predicted. The maximum number of cascaded junctions in this system can be determined in terms of a desired frequency bandwidth and allowable deviation in divided power.

This paper describes multi-branch Wilkinson power dividers using multilayer MMIC technology. Circuit configuration is simplified and the circuit area is effectively minimized using thin film microstrip lines. An impedance transformer between the input port and the divided point is introduced to complete impedance matching and reduce insertion loss in multi-branch power dividers. Size-reduced planar-type 2-, 4-, and 8-branch Wilkinson power dividers are produced and performed well.

The authors propose a waveguide π-junction with an inductive post for the element of a multiple-way power divider in a single-layered slotted waveguide array. This π-junction splits part of the power into two branch waveguides through one coupling window, and can excite densely arrayed waveguides at equal phase and amplitude. The power dividing characteristics are analyzed by Galerkin's method of moments and are confirmed experimentally. Reflection from the π-junction is suppressed to the level below 30 dB over 5.4% bandwidth by attaching an inductive post.