This paper describes a novel Wilkinson power divider operating at two arbitrary different frequencies. The proposed divider consists of two-section transmission lines and a series RLC circuit connected between two output ports. The circuit parameters for a dual-band operation are derived by the even/odd mode analysis. Equal power split, complete matching, and good isolation between two output ports are numerically demonstrated. Dual-band and broadband Wilkinson power dividers can be successfully designed. Finally, verification of this design method is also shown by electromagnetic simulations and experiments.

Three miniaturized lumped-element power dividers with a filtering function for use in quadrature mixers are described. Simulation results showed that they can be miniaturized, as compared to conventional ones with open/short stubs, while maintaining the filter characteristics. A fabricated 0.95-GHz 0power divider with a filtering function had a chip size about half that of a conventional lumped-element one. Its insertion loss at 0.950.05 GHz was 4.00.1 dB.

A new dual-band operation scheme is proposed for the Wilkinson power divider. The proposed structure has an open stub at the input and its two output ports are extended through a transmission line section. It offers improved bandwidth performance in the dual-band operation along with some structural advantages.

A two-quadrant CMOS current-mode plug-in divider using a compact 1/x device is presented. The mismatch errors of 1/x device cancel part of mismatch errors of the proposed divider. The simulation results indicate that the plug-in divider is feasible by the proposed approximation method. The adjustable 1/x device could be applied in difference ranges.

Novel low phase noise quadrature voltage-controlled oscillator (QVCO) and quadrature injection locked frequency divider (QILFD) with two coupled Hartley VCOs are proposed and implemented using the standard TSMC 0.18 µm CMOS 1P6M process. The QVCO employs pMOS as the core to reduce the up-conversion of low-frequency device noise to RF phase noise. It uses super-harmonic coupling technique to couple two differential Hartley VCOs and four small-size coupling transistors to set the directivity of quadrature output phases. At the 1.7 V supply voltage, the output phase noise of the QVCO is -124 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 4.12 GHz, and the figure of merit is -185 dBc/Hz. At the supply voltage of 1.7 V, the total power consumption is 13.1 mW. At the supply voltage of 1.5 V, the tuning range of the free-running QILFD is from 2.05 GHz to 2.36 GHz, about 310 MHz, and the locking range of the ILFD is from 3.99 to 5.19 GHz, about 1.20 GHz, at the injection signal power of 0 dBm.

The center-feed in a single-layer slotted waveguide array[1]-[3] is one of the key components in polarization division duplex (PDD) wireless systems. Two center-feed arrays with orthogonal polarization and boresight beams are orthogonally arranged side-by-side for transmission and reception, simultaneously. Each antenna has extremely high XPD (almost 50 dB in measurement) and a very high isolation (over 80 dB in measurement) between two arrays is observed provided the symmetry of slot arrangement is preserved [4]. Unfortunately, the area blocked by the center feed causes high sidelobe levels. This paper proposes the ridged cross-junction multiple-way power divider for realizing blockage reduction and symmetrical slot arrangement at the same time.

This paper proposes a wide-locking range divide-by-3 frequency divider employing 3D helical inductors fabricated in the 0.18-µm 1P6M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled NMOSFETs, and the LC resonator is composed of two 3D helical inductors and varactors. The aim of using 3D inductor is to reduce chip size. At the supply voltage of 1.2 V, the divider free-running frequency is tunable from 2.1 GHz to 2.6 GHz, and at the incident power of 0 dBm the locking range is about 2.11 GHz (29.16%), from the incident frequency 5.99 GHz to 8.1 GHz. The core power consumption is 4.56 mW. The die area is 0.6640.831 mm2.

An unequal Wilkinson power divider with adjustable power dividing ratio is proposed. The proposed power divider consists of rectangular defected ground structure (DGS), isolated island in DGS, and varactor diodes. The impedance of the microstrip line greatly increases due to the DGS, and varies because of the varying capacitance of diodes. The measured unequal dividing ratios vary from 1.97-13.4 and 2.25-10.6 when 2- and 4-diodes are adopted.

This paper presents a quadrature injection locked frequency divider (ILFD) employing tunable active inductors (TAIs), which are used is to extend the locking range and to reduce die area. The CMOS ILFD is based on a new quadrature voltage-controlled oscillator (VCO) with cross-coupled switching pairs and TAI-C tanks, and was fabricated in the 0.18-µm 1P6M CMOS technology. The divide-by-2 LC-tank ILFD is performed by adding injection MOSFETs between the differential outputs of the VCO. Measurement results show that at the supply voltage of 1.8 V, the divider free-running frequency is tunable from 1.34 GHz to 3.07 GHz, and at the incident power of 0 dBm the locking range is about 6 GHz (137%), from the incident frequency 1.37 GHz to 7.38 GHz. The core power consumption is 22.8 mW. The die area is 0.630.55 mm2.

A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N-1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the overall fractional division. The dual-modulus divider introduces a delay-locked-loop network to achieve phase compensation. Operating at the frequency of 3.2 GHz, the measured peak power reduction is around 16 dB for a deviation of 0.37% and a frequency modulation of 33 kHz. The circuit occupies 1.41.4 mm2 in a 0.18-µm CMOS process and consumes 52 mW.

A current-mode squarer/divider circuit with a novel translinear cell is presented for automotive applications. The proposed circuit technique increases the accuracy of the squarer/divider function with better input dynamic range and temperature insensitivity. Simulation results show that the variation of the output current is within ±0.2% over the temperature range from -40 to 140.

This paper describes a miniaturized in-phase power divider with a DC block function. We first propose three types of miniaturized in-phase power dividers composed of two distributed transmission lines, a resistor, and three capacitors to function as a DC block. Then, we use a simulation to compare the dividers. The simulation results show that, by properly selecting circuit configuration, we both achieve broadband frequency characteristics and miniaturize circuitry as compared to the conventional Wilkinson power divider with two DC block capacitors. Finally, an experimental UHF power divider fabricated to test the design concept is presented. Over the frequency range from 0.44 to 0.66 GHz, the experimental power divider exhibits power splits of -3.20.2 dB, return losses greater than 20 dB, and isolation between output ports greater than 20 dB.

This paper describes miniaturized broadband lumped-element in-phase power dividers. We first propose two types of miniaturized broadband lumped-element in-phase power dividers composed of two inductors, a resistor, and two capacitors. Next, we use a simulation to compare these dividers with conventional power dividers. The simulation results reveal that the proposed lumped-element in-phase power dividers can help miniaturize circuits (by decreasing inductances by about 30%, reducing the number of necessary capacitors by half, and decreasing necessary capacitances by about 30% as compared to conventional lumped-element dividers) and attain broadband frequency characteristics (by increasing normalized operating frequency bandwidths (f/f0) by about 80% as compared to conventional lumped-element dividers).

This paper presents a design method of multi-stage, multi-way microstrip power dividers with the aim of constructing a compact low-loss power divider with numbers of outputs. First, an integration design technique of power dividers composed of multi-step, multi-furcation and mitered bends is described. Since the analytical technique is founded on the planar circuit approach combined with the segmentation method, the optimization of the circuit patterns can be performed in a reasonable short computation time. Next, the present method is applied to the design of broadband Nn-way power dividers such as 32-way power divider consisting of 3-way dividers in two-stage structures, respectively. In addition, a 12-way power divider constructed from a series connection of a 3-way and three 4-way dividers is designed. The dividers equivalently contain a 3-section Chebyshev transformer to realize broadband properties. As a result, the fractional bandwidths of nearly 85% and 66.7% for the power-split imbalance less than 0.2 dB and the return loss better than -20 dB are obtained for the 9- and 12-way power dividers, respectively. The validity of these design results is confirmed by a commercial em-simulator (Ansoft HFSS) and experiments.

In deep sub-micrometer CMOS process, owing to the thin gate oxide and small subthreshold voltage, the leakage current becomes more and more serious. The leakage current has made the impact on phase-locked loops (PLLs). In this paper, the compensation circuits are presented to reduce the leakage current on the charge pump circuit and the MOS capacitor as the loop filter. The proposed circuit has been fabricated in 0.13-µm CMOS process. The power consumption is 3 mW and the die area is 0.270.3 mm2.

In this paper, a three-way divider is proposed for a partially-corporate feed in an alternating phase-fed single-layer slotted waveguide array. The divider is placed at the middle of the feed waveguide and reduces the long line effects; the frequency bandwidth is doubled. It is a kind of cross junction with one input port and three output ports; most of the power is equally divided into the right and left halves of the feed waveguide while the rest of power goes straight into the center radiating waveguide. Based upon the moment method design of the three-way divider, an inductive post is introduced for wide band power dividing control to the radiating waveguide. Reflection is below -20 dB over a wide bandwidth of 24.3-26.3 GHz, and the range of power dividing ratio ranges from 1/43 to 1/4. The amplitude and the phase from the two output ports to the feed waveguide are well balanced, and the differences are less than 0.1 dB and 5.0 degrees, respectively. The MoM analysis and the wide band design are verified experimentally in the 4 GHz band.

A novel asymmetric tapered-line power divider is presented. It has several strip resistors which are formed like a ladder between the tapered-line conductors to achieve a good output isolation. The equivalent circuits are derived with the even/odd-mode analysis. These equivalent circuits are employed to design the asymmetric power divider. The fabricated asymmetric power divider with 1:2 power dividing ratio shows broadband performances in return loss and isolation which are greater than 19 dB over a 3:1 bandwidth in the C-Ku bands.

A post-wall waveguide slot array with a three-way power divider on a single-layer substrate is designed to have a H-plane sectoral beam and an E-plane cosecant pattern with null-filling. Experiments in the 26 GHz band confirmed the sectoral beam with a -3 dB beam width of 117 deg and a ripple width of 2 dB in the sector.

This paper treats multi-way microstrip power dividers composed of multi-step, multi-furcation, and corners. Since the design procedure is founded on the planar circuit approach in combination with the segmentation method, optimization of the circuit configuration can be performed in a reasonable short computation time when applying the Powell's optimization algorithm. Actually, broadband 3- and 4-way power dividers with mitered bends are designed, and fractional bandwidths of about 90% and 100% are realized for the power-split imbalance less than 0.2 dB and the return loss better than -20 dB, respectively. The validity of the design results is confirmed by an EM-simulator (HFSS) and experiments.

In this paper, a novel CMOS defuzzification circuit using dual-output current conveyors (DO-CCII) is introduced. The behaviour of the proposed circuit has been verified with PSPICE using the models for 1.2 µm MIETEC CMOS process. The proposed circuit offers high-speed operation and high accuracy because of using second generation current conveyors (CCII). The designed circuit is suitable for fuzzy logic controllers using center of gravity (COG) defuzzification method.