In this paper, we present a modified image rejection method that uses imbalance compensation techniques for phase and gain in low-intermediate frequency (IF) software-defined radio (SDR) receivers. In low-IF receivers, the image frequency signal interferes with the desired signal owing to the phase and gain imbalances caused by analog devices. Thus, it is difficult to achieve the required image rejection ratio (IRR) of over 60dB without compensation. To solve this problem, we present modified blind compensation techniques based on digital signal processing using a feedback control loop with a practical computation process. The modified method can reduce the complexity when a hardware logic circuit is used, like an FPGA. The simulation and experimental results verify that the modified method achieves an IRR greater than 50-60dB for both the carrier and the modulated waves.

A LNA, an RF front-end and a 6th–order complex BPF for reconfigurable low-IF receivers are demonstrated in this work. Due to the noise cancellation, the two-stage LNA presents a low NF of 2.8 to 3.3 dB from 0.8 to 6 GHz. Moreover, the LNA delivers two kinds of gain curves with IIP3 of -2.6 dBm by employing the capacitive degeneration and the resistive gain-curve shaping in the second stage. The flicker noise corner frequency of the down-converter has been considered and the measured fC of the RF front-end is 200 kHz. The RF front-end also provides two kinds of gain curves. For the low-frequency mode, the conversion gain is 28.831.1 dB from 800 MHz to 2.4 GHz. For the high-frequency mode, the conversion gain is 26.827.4 dB from 3 to 5 GHz. The complex BPF is realized with gm-C LPFs by shifting the low-pass frequency response. With variable transconductances and capacitors, a fixed ratio of the centre frequency to the bandwidth (2) is achieved by varying the bandwidth and the centre frequency of the LPF simultaneously. The complex BPF has a variable bandwidth from 200 kHz to 6.4 MHz while achieving an image rejection of 44 dB.

A fifth-order switched-capacitor (SC) complex filter was implemented in 0.2-µm CMOS technology. A novel SC integrator was developed to reduce the die size and current consumption of the filter. The filter is centered at 24.730.15 kHz (3δ) and has a bandwidth of 20.260.3 kHz (3δ). The image channel is attenuated by more than 42.6 dB. The in-band third-order harmonic input intercept point (IIP3) is 17.3 dBm, and the input referred RMS noise is 34.3 µVrms. The complex filter consumes 350 µA with a 2.0-V power supply. The die size is 0.578 mm2. Owing to the new SC integrator, the filter achieves a 27% reduction in die size without any degradation in its characteristics, including its noise performance, compared with the conventional equivalent.

This letter presents an efficient multichannel low-IF reception scheme that improves digital communication quality in the sense of BER performance. Created by simply adding cosine rolloff filters to the conventional multichannel receiver, the proposed receiver achieves much higher accuracy than the conventional one.

In this paper an adjacent channel interference (ACI) cancellation scheme with undersampling for multi-channel reception is proposed and investigated. Low-IF receiver architecture is used in the multi-channel reception scheme. In this system, signal in the adjacent channel causes interference to the desired signal. The ACI cancellation scheme with analog filter bank has been proposed to mitigate the influence from the adjacent channel [10]. Undersampling technique is applied in this system in order to lower the required sampling frequency and power consumption. The effects of the adjacent channel to the undersampling technique in this scheme is examined and discussed.

In this paper a new adjacent channel interference (ACI) cancellation scheme for multi-channel signal reception with low-IF receivers is investigated through the experiment. In the low-IF receivers, the signal in the mirror frequency causes interference to the desired signal. In the proposed analog-digital signal processing scheme, channel selection is made by analog complex band pass filter and the signal is reconstruct by Wiener filter to eliminate the interference effect in order to improve the performance.

In this paper an analog-digital signal processing scheme for multichannel signal reception with low-IF receivers is proposed and its performance is investigated. In the low-IF receivers, the signal in the mirror frequency causes interference to the desired signal. In the proposed analog-digital signal processing scheme, the interference signal is extracted with the analog filter and the interference to the desired signal is reconstructed by LMS algorithm.

We have proposed a new low-IF transceiver architecture to simultaneously achieve both a small chip area and good minimum input sensitivity. The distinctive point of the receiver architecture is that we replace the complicated high-order analog filter for channel selection with the combination of a simple low-order analog filter and a sharp digital band-pass filter. We also proposed a high-speed convergence AGC (automatic gain controller) and a demodulation block to realize the proposed digital architecture. For the transceiver, we further reduce the chip area by applying a new form of direct modulation for the VCO. Since conventional VCO direct modulation tends to suffer from variation of the modulation index with frequency, we have developed a new compensation technique that minimizes this variation, and designed the low-phase noise VCO with a new biasing method to achieve large PSRR (power-supply rejection ratio) for oscillation frequency. The test chip was fabricated in 0.35-µm BiCMOS. The chip size was 3 3 mm2; this very small area was realized by the advantages of the proposed transceiver architecture. The transceiver also achieved good minimum input sensitivity of -85 dBm and showed interference performance that satisfied the requirements of the Bluetooth standard.

This paper describes a full-CMOS single-chip Bluetooth LSI fabricated using a 0.18 µm CMOS, triple-well, quad-metal technology. The chip integrates radio and baseband, which is compliant with Bluetooth Core Specification version 1.1. A direct modulation transmitter and a low-IF receiver architecture are employed for the low-power and low-cost implementation. To reduce the power consumption of the digital blocks, it uses a clock gating technique during the active modes and a power manager during the low power modes. The maximum power consumption is 75 mW for the transmission, 120 mW for the reception and 30 µW for the low power mode operation. These values are low enough for mobile applications. Sensitivity of -80 dBm has been achieved and the transmitter can deliver up to 4 dBm.

This paper presents a technique for improving the SNR and resolution of complex bandpass ΔΣADCs which are used for wireless communication systems such as cellular phone, wireless LAN and Bluetooth. Oversampling and noise-shaping are used to achieve high accuracy of a ΔΣAD modulator. However when a multi-bit internal DAC is used inside a modulator, nonlinearities of the DAC are not noise-shaped and the SNR of the ΔΣADC degrades. For the conversion of complex intermediate frequency (IF) input signals, a complex bandpass ΔΣAD modulator can provide superior performance to a pair of real bandpass ΔΣAD modulators of the same order. This paper proposes a new noise-shaping algorithm--implemented by adding simple digital circuitry--to reduce the effects of nonlinearities in multi-bit DACs of complex bandpass ΔΣAD modulators. We have performed simulation with MATLAB to verify the effectiveness of the algorithm, and the results show that the proposed algorithm can improve the SNR of a complex bandpass ΔΣADC with nonlinear internal multi-bit DACs.

In this paper, a digital compensation scheme for coefficient errors of a complex filter bank parallel A/D converter in low-IF receivers is presented. The complex filter bank is employed to suppress DC offset and image signals in the low-IF receivers and relax the requirements on the conversion rate and resolution of A/D converters. The proposed compensation scheme regenerates interference due to coefficient errors and subtracts it from the digital signal converted by an A/D converter. The proposed scheme also improves the effective resolution of A/D converters.

A broadband and flexible receiver architecture is investigated for the handheld software defined radio (SDR). The proposed SDR architecture is based on the direct conversion and low intermediate frequency (low-IF) principle with digital channel filtering, which provides the receiver with flexibility for the multi-standard application. This architecture also enables analog-to-digital converter activating essentially in baseband or low frequency so that the clock jitter, which serves as an important subject in the well-known IF sampling method, can be reduced. Basic performance of the proposed architecture has been confirmed by the experimental model.