This paper describes an overview of demands on wireless communications from the point of view of robotics, oceanics and aviation technologies. These technologies are mostly applied to extreme environments, where humans cannot easily approach and directly operate equipment. In such environments, reliable and robust wireless communications are highly required to perform missions perfectly. However, there are many issues for wireless technologies to meet those requirements due to poor propagation and large delay conditions. This paper discusses wireless communication technologies required in land-sea-and-air environments based on the recent development challenges of unmanned ground and marine robots and next-generation air-transportation systems. This paper will contribute future wireless communication techniques for unmanned robots and next-generation aviations.

This paper presents a single-chip RF tuner/OFDM demodulator for a mobile digital TV application called “1-segment broadcasting.” To achieve required performances for the single-chip receiver, a tunable technique for a low-noise amplifier (LNA) and spurious suppression techniques are proposed in this paper. Firstly, to receive all channels from 470 MHz to 770 MHz and to relax distortion characteristics of following circuit blocks such as an RF variable-gain amplifier and a mixer, a tunable technique for the LNA is proposed. Then, to improve the sensitivity, spurious signal suppression techniques are also proposed. The single-chip receiver using the proposed techniques is fabricated in 90 nm CMOS technology and total die size is 3.26 mm 3.26 mm. Using the tunable LNA and suppressing undesired spurious signals, the sensitivities of less than -98.6 dBm are achieved for all the channels.

In Perosonal communication systems (PCS), reduction control of call blocking rate on wireless-environments, especially in terminating-call set up, is one of the key technologies to design network architecture. This is because the error rate of transferred messages there is normally much higher than that in wired environments. Terminating-call reforwarding technologies, to forward twice terminating-call messages through paging channels depending on call states, would be essential under such conditions, and in the PCS network architecture there are two possible reforwarding schemes: network-assisted reforwarding (NAR) and cell-station-assisted reforwarding (CAR). We first propose a traffic model for evaluating the performance of terminating-call reforwarding from the viewpoint of reduction of the call blocking rate on PCS, and then we clarify the advocating domains for NAR and CAR. Finally, we present a case study using this evaluation model for the Personal Handy-phone System (PHS), which is a PCS in Japan. The results of this study confirm that NAR is more efficient than CAR.

The demand for data communication over Personal Handy-phone System (PHS) is expected to rapidly increase in the near future. Some applications based on the circuit-switched services have been recently developed. However, the packet-switched service is better than the circuit-switched service for personal data communications in terms of the flexible utilization of radio resources. In this paper, we propose PHS with packet data communications system (PHS-PD), which has four system concepts; (i) to supprot the Internet access, (ii) to realize compatibility with circuit-switching services, (iii) to share the common radio channels with circuit-switched calls, and (iv) to utilize idle time slots for packet data. Moreover, a novel packet channel structure for sharing radio resources with circuit-switched calls is introduced. Although packet data are transferred using common radio resources, the proposed channel structure prevents any degradation in call loss performance of the circuit-switching service. An evaluation of the maximum packet transmission rate shows that PHS-PD can offer a data communication rate of 20.1 kbps even if circuit-switched calls are in progress. Furthermore, up to 83.6 kbps is possible if circuit-switched calls are quiescent. It is also shown that enough capacity for a practical e-mail service can be ensured by PHS-PD even if the degradation of throughput performance due to packet collisions on random access channels is considered.

A fully differential direct conversion receiver IC for W-CDMA is presented. The receiver IC consists of an LNA, a quadrature demodulator, low-pass filters (LPFs), and variable gain amplifiers (VGAs). In order to suppress DC offset, which is the most important issue in a direct conversion system, an active harmonic mixer is applied to the quadrature demodulator. Furthermore, a receiving system, including the LNA and an RF filter, adopts a differential architecture to reduce local signal leakage, which generates DC offset. Performance of the entire receiving system was evaluated and DC offset in steady state was measured at only 40 mV. Moreover, DC offset variation at the LNA gain change, which has the largest affect on the receiving performance, was limited to 70 mV, which is less than -10 dB compared to desired signal strength. It was confirmed by computer simulation that the DC offset variation at the LNA gain change did not degrade bit error rate (BER) performance at all.

The low-frequency output noise that is caused by introducing random-switching control into DC-to-DC converters with output regulation, is discussed quantitatively. A modified converter model involving the unintended effect of random switching is derived from the consideration of noise-generation mechanism. After the theoretical analysis based on the model, it is clarified that the magnitude of output noise is in proportion to the variance of switching interval. The experimental results of a buck-type converter are compared with those obtained theoretically, so that the validity of the theoretical results is confirmed experimentally.

Application of multipled block codes (MBCs) for realizing new flexible and efficient transmission systems that feature in hunting-free reframing and asynchronous multiplexing is investigated. First, the principles of MBC are overviewed to show the capacities of filterless clock recovery. Then it is shown that modification of simple frame structure of MBC line code can be used for attaining hunting-free reframing for multiplexing systems. Two types of MBCs are developed to this end. While the one uses header blocks for hunting-free reframing, the other uses distributed frame patterns. Header design of multipled block codes (MBC) for hunting-free reframing (HFR) is investigated for frame patterns with and without violation compensation. The feasibility of hunting-free reframing is tested in an experimental system. Application of hunting-free reframing to asynchronous multiplexing is also investigated and tested in an experimental system. Finally, advantages of hunting-free multiplexing systems are discussed.

The architecture and control procedure for a direct conversion receiver are investigated for a linear modulation scheme. The proposed design techniques maintain receiver linearity despite various types of signal distortion. The techniques include the fast gain control procedure for receiving a control channel for air interface connection, DC offset canceling in both analog and digital stages, and 2nd-order intermodulation distortion canceling in an analog down-conversion stage. Experimental and computer simulation results on PHS (Personal Handy-phone System) parameters, showed that required linear modulation performance was achieved and thus the applicability of the proposed techniques was demonstrated.

A direct conversion receiver for W-CDMA, which consumes extremely low power, is presented. The receiver consists of a low-noise amplifier (LNA) IC, a receiver IC and other passive components such as an RF-SAW (Surface Acoustic Wave) filter. The receiver IC includes a quadrature demodulator (QDEM) with a local oscillator (LO) divider, low-pass filters (LPFs) for channel selection, variable gain amplifiers (VGAs) with dynamic range of 80 dB, and a fractional-N synthesizer. The power consumption for the entire receiver chain was only 30.8 mA at supply voltage of 2.7 V.

PLL timing design techniques introduced here feature (1) a word-line resetting-equalization scheme for reducting the access time and the memory cell current, (2) a cyclic input buffer power-cutting scheme to reduce the excess power in low-frequency operation, and (3) a super-pipelined parallel test scheme which allows the evaluation of high-speed LSIs by low-speed LSI testers to reduce the test costs. These techniques successfully contribute to the development of a 7 ns GTL I/O 16 Mb BiCMOS SRAM LSI.

In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.

This paper presents the evaluation for personal communication systems (PCS). Two types of PCS are supposed for low and high degree of mobility. The service area with 30km radius is covered by a multiple hexagonal cells, which are micro cells and macro cells for the low mobility and high mobility planes respectively. As for a traffic distribution, uniform and exponentially tapered traffic distributions are assumed. After defining the system model, cost evaluation form along with capacity has been derived. The evaluation and discussions are made in terms of cost economy, capacity and spectrum usage in various conditions. It is shown that there exist the optimum cell radius for the prescribed subscriber numbers and the integration of two systems is desirable for the support of full mobility with cost-effectiveness and spectrum efficiency.

This paper proposes novel feedforward architecture of the second-order multibit ΔΣAD modulator with single DAC-feedback topology. The ΔΣAD modulator realizes high resolution by oversampling and noise shaping techniques. However, its SNDR (Signal to Noise and Distortion Ratio) is limited by the dynamic range of the input signal and non-idealities of circuit building blocks, particularly by the harmonic distortion in amplifier circuits. A full feedforward ΔΣAD modulator structure has the signal transfer function of unity under ideal circumstances, which means that the signal swings through the loop filter become smaller compared with a feedbacked ΔΣAD modulator. Therefore, the harmonic distortion generated inside the loop filter can be significantly reduced in the feedforward structure because the effect of non-idealities in amplifiers can be suppressed when signal swing is small. Moreover, the reduction of the internal signal swings also relaxes output swing requirements for amplifiers with low supply voltage. However, in conventional feedforward ΔΣAD modulator, an analog adder is needed before quantizer, and especially in a multibit modulator, an additional amplifier is necessary to realize the summation of feedforward signals, which leads to extra chip area and power dissipation. In this paper, we propose a novel architecture of a feedforward ΔΣAD modulator which realizes the summation of feedforward signals without additional amplifier. The proposed architecture is functionally equivalent to the conventional one but with smaller chip area and lower power dissipation. We conducted MATLAB and SPICE simulations to validate the proposed architecture and modulator circuits.

A fully-integrated system-on-chip (SoC) for Bluetooth Low Energy (BLE) with 3.2mA RX and 3.5mA TX current consumption is presented. To achieve both low current consumption and high performance, the SoC employs a sliding-IF architecture with high tolerance against out-of-band-blocking signals, a power management unit with improved efficiency, and techniques to reduce current in core circuits. The SoC achieves RX sensitivity of -93dBm and maximum output power of 0dBm. The SoC is in compliance with version 4.2 of the Bluetooth specifications and with the radio regulations of the FCC, ETSI, and ARIB. The SoC achieves the minimum level of current consumption for both RX and TX modes in the published product-level SoCs.

In developing the SXO operating system for the SURE SYSTEM 2000 continuous operation system, we aimed to create an unprecedentedly high software and hardware fault tolerance. We devised a fault tolerant architecture and various methodologies to ensure fault tolerance. We implemented these techniques systematically throughout operating system development. In the design stage, we developed a design methodology called the recovery process chart to verify that recovery mechanisms were complete. In the manufacturing stage, we applied the concept of critical routes to recovery and other processes essential to high dependability. We also developed a method of finding critical routes in a recovery process chart. In the test stage, we added an artificial software fault injection mechanism to the operating system. It generates various reproducible errors at appropriate times and reduces the number of personnel needed for test, making system reliability evaluation easy.

Recently, the Doherty amplifier technique has been the focus of attention not only for base stations but also for mobile terminals because of its high power-added efficiency in the large back-off region. In this paper, we present a miniaturized Doherty power amplifier (PA) module for W-CDMA mobile terminals. The developed Doherty PA module consists of a 4-mm-square ceramic substrate (4.0 mm4.0 mm1.5 mm, alumina, dielectric constant = 8.8), a 1-mm-square GaAs MMIC (1.0 mm1.0 mm0.1 mm), and 0603-size SMD passive components. To miniaturize the module size, the optimal designed quarter-wavelength transmission lines, which are used for impedance conversion for carrier amplifier output and phase compensation for peak amplifier input, are embedded in the ceramic module substrate. Two GaAs HBTs for a carrier amplifier and a peak amplifier and base bias circuits for each amplifier are integrated onto a single-chip GaAs MMIC. Measurement results at 1950 MHz in a W-CDMA uplink signal indicate that 27 dBm of the maximum output power, 45% of the power-added efficiency (PAE), 11 dB of power gain, and 43% of PAE at 6 dB back-off, i.e. 24 dBm output power, are obtained with the developed Doherty PA. In other words, the PAE is improved from the theoretical PAE of a conventional class B amplifier, namely, from 23% to 43%. This is the smallest Doherty amplifier developed in the form of a module for mobile terminals.

A broadband and flexible receiver architecture is investigated for the handheld software defined radio (SDR). The proposed SDR architecture is based on the direct conversion and low intermediate frequency (low-IF) principle with digital channel filtering, which provides the receiver with flexibility for the multi-standard application. This architecture also enables analog-to-digital converter activating essentially in baseband or low frequency so that the clock jitter, which serves as an important subject in the well-known IF sampling method, can be reduced. Basic performance of the proposed architecture has been confirmed by the experimental model.

This paper presents a miniaturized dual-mode Doherty PA module applicable for an HPSK signal and an OFDM 64-QAM signal. Dual-mode operation with identical hardware is realized by introducing a bias switching technique, which changes bias conditions of amplifiers according to transmission signals, and employing dual-mode matching circuits, which are designed based on the results of load-pull measurements using an HPSK signal and an OFDM 64-QAM signal. The Doherty PA module consists of a Doherty stage and a gain stage. Two GaAs-HBTs for a Doherty stage and one GaAs-HBT for a gain stage are integrated onto a 1 mm-square single GaAs-MMIC. In the HPSK mode, maximum output power of 26.7 dBm, power added efficiency (PAE) of 41%, and power gain of 27 dB are obtained in the condition that adjacent channel leakage power ratio (ACLR) is under -38 dBc. In the OFDM 64-QAM mode, maximum output power of 21.0 dBm, PAE of 27%, and power gain of 28 dB are obtained under EVM < 3.0%. This is the first multi-mode Doherty PA module suitable for multi peak to average power ratio (PAPR) signals.