In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.

A wideband noise-cancelling receiver front-end is proposed in this brief. As a basic architecture, a low-noise transconductance amplifier, a passive mixer, and a transimpedance amplifier are employed to compose the wideband receiver. To achieve wideband input matching for the transconductor, a global feedback method is adopted. Since the wideband receiver has to minimize linearity degradation if a large blocker signal exists out-of-band, a linearization technique is applied for the transconductor circuit. The linearization cancels third-order intermodulation distortion components and increases linearity; however, the additional circuits used in linearization generate excessive noise. A noise-cancelling architecture that employs an auxiliary path cancels noise signals generated in the main path. The designed receiver front-end is fabricated using a 65-nm CMOS process. The receiver operates in the frequency range of 25 MHz-2 GHz with a gain of 49.7 dB. The in-band input-referred third-order intercept point is improved by 12.3 dB when the linearization is activated, demonstrating the effectiveness of the linearization technique.

A 0.13-µm CMOS 2.4-GHz low-noise balun-mixer is proposed, where a noise-canceling transconductance stage is adopted for low-noise characteristics. A current-bleeding circuit with an LC resonator is also adopted to further improve the noise figure of the proposed balun-mixer, without additional DC power consumption. The measured results show a DSB NF of 5.5 dB over output IF frequency ranges of 10 to 100 MHz, a conversion gain of 19 dB, and an input P1 dB of -16 dBm. The proposed balun-mixer is implemented in 0.13-µm CMOS technology and consumes only 4.5 mA from a 1.5-V supply voltage.