In this paper, Epitaxial (Epi) Junction Termination Extension (JTE) technique for silicon carbide (SiC) power device is presented. Unlike conventional JTE, the Epi-JTE doesn't require high temperature (about 500°C) implantation process. Thus, it doesn't require high temperature (about 1700°C) process for implanted dose activation and surface defect curing. Therefore, the manufacturing cost will be decreased. Also, the fabrication process is very simple because the dose of the JTE is controlled by epitaxy growth. The blocking characteristic is analyzed through 2D-simulation for the proposed Epi-JTE. In addition, the effect was validated by experiment of fabricated SiC device with the Single-Zone-Epi-JTE. As a result, it has blocking capability of 79.4% compared to ideal parallel-plane junction breakdown.

Next generation advanced power devices show remarkable progress in wide band-gap power devices such as silicon carbide and gallium nitride devices, as well as novel silicon devices called as super junction FETs and so on. The future direction of power electronics applications is surveyed in terms of output power density as an index of future power electronics development, instead of the power conversion efficiency, taking the device progress in sight. Over the last 30 years, the output power density of power electronics apparatuses has increased by a factor of two figures. New markets, such as a power supply for future generation CPU, a compact unit inverter and a electric vehicle-driving inverter unit, are expected to grow rapidly from 2010 to 2015 with the advance in the out power density of power converter. The possibility of power electronics innovation with progress in the output power density will be discussed in conjunction with development of next generation advanced power devices and related technologies.

An InGaP/GaAs composite channel has been proposed in order to improve the electron transport properties of InGaP for high power device applications. The electron mobility and velocity are increased due to the contribution of high mobility GaAs. Although the composite channel FET shows higher transconductance and drain current than those of the InGaP single channel FET, the breakdown voltage is nearly the same. The composite channel FET delivered output power of 0.6 W/mm with power added efficiency of 46.2% under 17 V operation at 1.9 GHz.

We review advances in GaN-based microwave power field-effect-transistors (FETs). Evolution in device technology included metal-semiconductor-field-effect-transistors (MESFETs), heterostructure-field-effect-transistors (HFETs), modulation-doped-field-effect-transistors (MODFETs) or high-mobility-transistors (HEMT), HEMTs with high Al contents, HEMTs with gate recess and GaN-channel HEMTs grown on SiC substrates. The power density was first reported as 1.1 W/mm at 2 GHz using an AlGaN/GaN HEMT structure grown on sapphire substrate, and was subsequently improved to 1.5-1.7 W/mm at 4-10 GHz by refinement in device structure and processing techniques. This was advanced to 2.6-3.3 W/mm at 8-18 GHz by adopting a high-Al-content AlGaN barrier layer. Success in gate recess helped to further increase the power density of these GaN HEMTs on sapphire substrates to 4.6 W/mm at 6 GHz. Substrate replacement of sapphire by SiC, for excellent thermal dissipation, has boosted performance to 6.9 W/mm at 10 GHz, which is higher than GaAs-based FETs by a factor of 6. Device periphery was scaled up to obtain high total output power. On one hand, GaN HEMTs on sapphire, using a flip-chip bonding technology for thermal management, have generated 7.6 W at 4 GHz. On another hand, GaN HEMTs on SiC, taking advantage of the high substrate thermal conductivity, have achieved 9.1 W at 7.4 GHz. Two types of initial GaN-based power amplifiers were also demonstrated using a flip-chip IC scheme. The transistors used were 0.7 to 0.8-µm-long-gate GaN HEMTs. Bandwidths of 1-8 GHz and 3-9 GHz were achieved with gains up to 11.5 dB. The output power levels ranged from 3.2 to 4.6 W using devices with 2 and 3-mm gate peripheries, which were higher than that achievable with GaAs-based HEMTs of the same size by a factor of 2. Traps in the device structure currently limit performance of most GaN FETs. These traps cause dispersion in the I-V characteristics, which increases knee voltage and reduces channel current under RF gate drive. However, they are believed to be not inherent in the GaN semiconductor system and can be minimized as the technology matures.

This paper describes novel techniques for analyzing power MOSFETs. Since the gate width of power MOSFETs is much larger than that of power MESFETs or HJFETs, an appropriate device design to suppress matching circuit losses is needed. These losses and the intrinsic device characteristics are analyzed employing the proposed techniques, which are based on large-signal simulations. Also, new formulas describing the dependence of saturated output power on gate width are derived to perform loss-minimized design. These techniques are applied to the design of power MOSFETs for GSM cellular telephones. As a result, an output power of 35.5 dBm with a power-added efficiency of 55% and a power gain of 10.5 dB at 900 MHz have been achieved.

This paper describes 950 GHz power performance of double-doped AlGaAs/InGaAs/AlGaAs heterojunction field-effect transistors (HJFET) operated at a drain bias voltage ranging from 2.5 to 3.5 V. The developed 1.0 µm gatelength HJFET exhibited a maximum drain current (Imax) of 500 mA/mm, a transconductance (gm) of 300 mS/mm, and a gate-to-drain breakdown voltage of 11 V. Operated at 3.0 V, a 17.5 mm gate periphery HJFET showed 1.4 W Pout and -50.3 dBc adjacent channel leakage power at a 50 kHz off-carrier frequency from 950 MHz with 50% PAE. Harmonic balance simulations revealed that the flat gm characteristics of the HJFET with respect to gate bias voltage are effective to suppress intermodulation distortion under large signal operation. The developed HJFET has great potential for small-sized digital cellular power applications operated at a low DC supply voltage.

We have developed new DMOS FET (DMOS) and intelligent power devices (IPD) specified for automotive load driving. Their features are extra-high surge immunity and low on-resistance. MOS power semiconductor devices are the most suitable for driving high speed and large current loads in future car electronics, but their high cost is the main obstacle preventing their implementation. To cut the total system cost, we have tried to enhance surge immunity of power semiconductor devices, at the same time reducing ON resistance, which enables us to omit external protection. Enhanced avalanche power dissipation also enables us to lower the breakdown voltage of the device, which also brings lower on-resistance. The drain to source avalanche immunity of vertical type DMOS (VDMOS) has been sharply improved by using the parasitic PN junction of the channel diffusion region as the cellular zener diode. Avalanche power dissipation energy per unit area of this durable DMOS is 10 to 100 times higher than that of conventional VDMOSs. Although the breakdown voltage of this device is only 30V, no external protection device is required in automotive applications. Several fault phenomena which might occur in this device are also described. Two types of IPDs are proposed in this paper. One is a durable and low-cost high-side switch IPD, whose enhanced surge immunity of IC section from VDD line transient is verified by prototypes. Simplification of the fabrication process has also been achieved by lowering its breakdown voltage. The other is an extra-low on-resistance H-bridge IPD. Major on-resistance reduction of an output lateral type DMOS (LDMOS) is achieved because the cell-array structure is realized by applying 2-layer electrode technology to the power section. The on-resistance per unit area of this LDMOS is almost equal to that of VDMOSs in the same voltage class.