In this paper, a nanopower supply-insensitive complementary metal-oxide-semiconductor (CMOS) unit threshold voltage (Vth) extractor circuit is proposed. It meets the contemporary industry demand for portable devices that operate with very low power consumption and small output sensitivity. An α times Vth (αVth) extractor is also described, in which α varies continuously. Both incremental and decremental αVth voltages are obtained. A post-layout simulation results using HSPICE with CMOS 0.18um process show that the proposed unit Vth extractor consumes 265nW of power given a 1.6V power supply. Sensitivity to temperature is 0.022%/°C ranging from 0°C to 100°C. Sensitivity to supply voltage is 0.027%/V.

A CMOS bandgap reference circuit without resistors, which can successfully operate under 1V supply voltage is proposed. The improvement is realized by the technique of the voltage divider and a new current source. The most attractive merit is that the proposed circuit breaks the bottleneck of low supply voltage design caused by the constant bandgap voltage value (1.25V). Moreover, the temperature coefficient of the reference voltage Vref is improved by compensating the temperature dependence caused by the current source. The simulation results using a standard CMOS 0.18 um process show that the value of Vref can be achieved around 0.5 V with a minimum supply voltage of 0.85 V. Meanwhile, the temperature coefficient of the output voltage is only 3.5ppm/°C from 0 °C to 70 °C.

This paper presents the design and implementation of a supply and process-insensitive 12-bit Digital Pulse Width Modulator (DPWM) for digital DC-DC converters. The DPWM is realized by a ring oscillator-based segmented tapped delay line and a counter-comparator. The number of delay cells required is reduced by employing a proposed delay cell reuse technique. The ring oscillator of the tapped delay line is made insensitive to supply and process variation by biasing the differential delay cells with a supply-insensitive replica bias circuit. Simulation results show that the variation of the switching frequency of the DPWM at 1.02 MHz is 0.4% for supply voltage variation between 1.5 V and 2.5 V and 0.95% over the temperature range from -40 to 90. Monte-Carlo simulation was also performed to account for the effect of mismatch between the transistors of the ring oscillator. The worst case delay of the delay cells is 0.87% for 5% (3-σ) mismatch. The design was fabricated in CMOS 0.18 µm process and the fabricated DPWM achieved a supply sensitivity of 0.82% and a current consumption of 14 µA.

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage (VOL) to be equal to the reference voltage (VOL.ref) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1 Gb/s. The worst-case variations of VOL.ref and VOL of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of 20 to 90 and a supply voltage range of 2.25 V to 2.75 V, while the worst-case variation of VOL of the conventional output driver was measured to be 24% within the same ranges of temperature and supply voltage.

A fully on-chip current controlled open-drain output driver using a bandgap reference current generator was designed for high bandwidth DRAMs. It reduces the overhead of receiving a digital code from an external source for the compensation of the temperature and supply voltage variations. The correct value of the current control register is updated at the end of every auto refresh cycle. The operation at the data rate up to 0.8 Gb/s was verified by SPICE simulation using a 0.22 µm triple-well CMOS technology.