This paper proposes a time-to-digital converter (TDC) utilizing the cascaded time difference amplifier (TDA) and shows measurement results with 0.18 µm CMOS. The proposed TDC operates in two modes, a wide input range mode and a fine time resolution mode. We employ a non-linearity calibration technique based on a lookup table. The wide input range mode shows 10.2 ps time resolution over 1.3 ns input range with DNL and INL of +0.8/-0.7LSB and +0.8/-0.4LSB, respectively. The fine time resolution mode shows 1.0 ps time resolution over 60 ps input range with DNL and INL of +0.9/-0.9LSB and +0.8/-1.0LSB, respectively.

We introduce a 16 × cascaded time difference amplifier (TDA) using a differential logic delay cell with 0.18 µm CMOS process. By employing the differential logic delay cell in the delay chain instead of the CMOS logic delay cell, less than 8% TD gain offset with 150 ps input range is achieved. The input referred standard deviation of the output time difference error is 2.7 ps and the input referred is improved by 17% compared with that of the previous TDA using the CMOS logic delay cell.