Cascaded Time Difference Amplifier with Differential Logic Delay Cell

Shingo MANDAI; Toru NAKURA; Tetsuya IIZUKA; Makoto IKEDA; Kunihiro ASADA

doi:10.1587/transele.E94.C.654

Cascaded Time Difference Amplifier with Differential Logic Delay Cell

Shingo MANDAI, Toru NAKURA, Tetsuya IIZUKA, Makoto IKEDA, Kunihiro ASADA

Full Text Views

0

Share
Cite this

Summary :

We introduce a 16 × cascaded time difference amplifier (TDA) using a differential logic delay cell with 0.18 µm CMOS process. By employing the differential logic delay cell in the delay chain instead of the CMOS logic delay cell, less than 8% TD gain offset with 150 ps input range is achieved. The input referred standard deviation of the output time difference error is 2.7 ps and the input referred is improved by 17% compared with that of the previous TDA using the CMOS logic delay cell.

Publication: IEICE TRANSACTIONS on Electronics Vol.E94-C No.4 pp.654-662

Publication Date: 2011/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E94.C.654

Type of Manuscript: PAPER

Category: Electronic Circuits

Cite this

Copy

Shingo MANDAI, Toru NAKURA, Tetsuya IIZUKA, Makoto IKEDA, Kunihiro ASADA, "Cascaded Time Difference Amplifier with Differential Logic Delay Cell" in IEICE TRANSACTIONS on Electronics, vol. E94-C, no. 4, pp. 654-662, April 2011, doi: 10.1587/transele.E94.C.654.
Abstract: We introduce a 16 × cascaded time difference amplifier (TDA) using a differential logic delay cell with 0.18 µm CMOS process. By employing the differential logic delay cell in the delay chain instead of the CMOS logic delay cell, less than 8% TD gain offset with 150 ps input range is achieved. The input referred standard deviation of the output time difference error is 2.7 ps and the input referred is improved by 17% compared with that of the previous TDA using the CMOS logic delay cell.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.654/_p

Copy

@ARTICLE{e94-c_4_654,
author={Shingo MANDAI, Toru NAKURA, Tetsuya IIZUKA, Makoto IKEDA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Cascaded Time Difference Amplifier with Differential Logic Delay Cell},
year={2011},
volume={E94-C},
number={4},
pages={654-662},
abstract={We introduce a 16 × cascaded time difference amplifier (TDA) using a differential logic delay cell with 0.18 µm CMOS process. By employing the differential logic delay cell in the delay chain instead of the CMOS logic delay cell, less than 8% TD gain offset with 150 ps input range is achieved. The input referred standard deviation of the output time difference error is 2.7 ps and the input referred is improved by 17% compared with that of the previous TDA using the CMOS logic delay cell.},
keywords={},
doi={10.1587/transele.E94.C.654},
ISSN={1745-1353},
month={April},}

Copy

TY - JOUR
TI - Cascaded Time Difference Amplifier with Differential Logic Delay Cell
T2 - IEICE TRANSACTIONS on Electronics
SP - 654
EP - 662
AU - Shingo MANDAI
AU - Toru NAKURA
AU - Tetsuya IIZUKA
AU - Makoto IKEDA
AU - Kunihiro ASADA
PY - 2011
DO - 10.1587/transele.E94.C.654
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - We introduce a 16 × cascaded time difference amplifier (TDA) using a differential logic delay cell with 0.18 µm CMOS process. By employing the differential logic delay cell in the delay chain instead of the CMOS logic delay cell, less than 8% TD gain offset with 150 ps input range is achieved. The input referred standard deviation of the output time difference error is 2.7 ps and the input referred is improved by 17% compared with that of the previous TDA using the CMOS logic delay cell.
ER -