A Design of Low Latency Random Access Preamble Detector for LTE Uplink Receiver

Joohyun LEE; Bontae KOO; Hyuckjae LEE

doi:10.1587/transcom.E96.B.1089

A Design of Low Latency Random Access Preamble Detector for LTE Uplink Receiver

Joohyun LEE, Bontae KOO, Hyuckjae LEE

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This paper presents a hardware design of high throughput, low latency preamble detector for 3GPP LTE physical random access channel (PRACH) receiver. The presented PRACH receiver uses the pipelined structure to improve the throughput of power delay profile (PDP) generation which is executed multiple times during the preamble detection. In addition, to reduce detection latency, we propose an instantaneous preamble detection method for both restricted and unrestricted set. The proposed preamble detection method can detect all existing preambles directly and instantaneously from PDP output while conducting PDP combining for restricted set. The PDP combining enables the PRACH receiver to detect preambles robustly even in severe Doppler effect or frequency error exist. Using proposed method, the worst case preamble detection latency time can be less than 1 ms with 136 MHz clock and the proposed PRACH receiver can be implemented with approximately 237k equivalent ASIC gates count or occupying 30.2% of xc6vlx130t FPGA device.

Publication: IEICE TRANSACTIONS on Communications Vol.E96-B No.5 pp.1089-1096

Publication Date: 2013/05/01

Publicized

Online ISSN: 1745-1345

DOI: 10.1587/transcom.E96.B.1089

Type of Manuscript: PAPER

Category: Transmission Systems and Transmission Equipment for Communications

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Joohyun LEE, Bontae KOO, Hyuckjae LEE, "A Design of Low Latency Random Access Preamble Detector for LTE Uplink Receiver" in IEICE TRANSACTIONS on Communications, vol. E96-B, no. 5, pp. 1089-1096, May 2013, doi: 10.1587/transcom.E96.B.1089.
Abstract: This paper presents a hardware design of high throughput, low latency preamble detector for 3GPP LTE physical random access channel (PRACH) receiver. The presented PRACH receiver uses the pipelined structure to improve the throughput of power delay profile (PDP) generation which is executed multiple times during the preamble detection. In addition, to reduce detection latency, we propose an instantaneous preamble detection method for both restricted and unrestricted set. The proposed preamble detection method can detect all existing preambles directly and instantaneously from PDP output while conducting PDP combining for restricted set. The PDP combining enables the PRACH receiver to detect preambles robustly even in severe Doppler effect or frequency error exist. Using proposed method, the worst case preamble detection latency time can be less than 1 ms with 136 MHz clock and the proposed PRACH receiver can be implemented with approximately 237k equivalent ASIC gates count or occupying 30.2% of xc6vlx130t FPGA device.
URL: https://globals.ieice.org/en_transactions/communications/10.1587/transcom.E96.B.1089/_p

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@ARTICLE{e96-b_5_1089,
author={Joohyun LEE, Bontae KOO, Hyuckjae LEE, },
journal={IEICE TRANSACTIONS on Communications},
title={A Design of Low Latency Random Access Preamble Detector for LTE Uplink Receiver},
year={2013},
volume={E96-B},
number={5},
pages={1089-1096},
abstract={This paper presents a hardware design of high throughput, low latency preamble detector for 3GPP LTE physical random access channel (PRACH) receiver. The presented PRACH receiver uses the pipelined structure to improve the throughput of power delay profile (PDP) generation which is executed multiple times during the preamble detection. In addition, to reduce detection latency, we propose an instantaneous preamble detection method for both restricted and unrestricted set. The proposed preamble detection method can detect all existing preambles directly and instantaneously from PDP output while conducting PDP combining for restricted set. The PDP combining enables the PRACH receiver to detect preambles robustly even in severe Doppler effect or frequency error exist. Using proposed method, the worst case preamble detection latency time can be less than 1 ms with 136 MHz clock and the proposed PRACH receiver can be implemented with approximately 237k equivalent ASIC gates count or occupying 30.2% of xc6vlx130t FPGA device.},
keywords={},
doi={10.1587/transcom.E96.B.1089},
ISSN={1745-1345},
month={May},}

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TY - JOUR
TI - A Design of Low Latency Random Access Preamble Detector for LTE Uplink Receiver
T2 - IEICE TRANSACTIONS on Communications
SP - 1089
EP - 1096
AU - Joohyun LEE
AU - Bontae KOO
AU - Hyuckjae LEE
PY - 2013
DO - 10.1587/transcom.E96.B.1089
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E96-B
IS - 5
JA - IEICE TRANSACTIONS on Communications
Y1 - May 2013
AB - This paper presents a hardware design of high throughput, low latency preamble detector for 3GPP LTE physical random access channel (PRACH) receiver. The presented PRACH receiver uses the pipelined structure to improve the throughput of power delay profile (PDP) generation which is executed multiple times during the preamble detection. In addition, to reduce detection latency, we propose an instantaneous preamble detection method for both restricted and unrestricted set. The proposed preamble detection method can detect all existing preambles directly and instantaneously from PDP output while conducting PDP combining for restricted set. The PDP combining enables the PRACH receiver to detect preambles robustly even in severe Doppler effect or frequency error exist. Using proposed method, the worst case preamble detection latency time can be less than 1 ms with 136 MHz clock and the proposed PRACH receiver can be implemented with approximately 237k equivalent ASIC gates count or occupying 30.2% of xc6vlx130t FPGA device.
ER -