Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture

Toru SHIMIZU; Masami NAKAJIMA; Masahiro KAINAGA

doi:10.1093/ietele/e89-c.11.1512

Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture

Toru SHIMIZU, Masami NAKAJIMA, Masahiro KAINAGA

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This paper describes the design and evaluation of a massively parallel processor base on Matrix architecture which is suitable for portable multimedia applications. The proposed architecture in this paper achieves 40 GOPS of 16-bit fixed-point additions at 200 MHz clock frequency and 250 mW power dissipation. In addition, 1 M-bit SRAM for data registers and 2,048 2-bit processing elements connected by a flexible switching network are integrated in 3.1 mm² in 90 nm low-power CMOS technology. The energy-efficient Matrix architecture supports 2,048-way parallel operations and the programmable functions required for multimedia SoCs.

Publication: IEICE TRANSACTIONS on Electronics Vol.E89-C No.11 pp.1512-1518

Publication Date: 2006/11/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e89-c.11.1512

Type of Manuscript: Special Section INVITED PAPER (Special Section on Novel Device Architectures and System Integration Technologies)

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Toru SHIMIZU, Masami NAKAJIMA, Masahiro KAINAGA, "Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture" in IEICE TRANSACTIONS on Electronics, vol. E89-C, no. 11, pp. 1512-1518, November 2006, doi: 10.1093/ietele/e89-c.11.1512.
Abstract: This paper describes the design and evaluation of a massively parallel processor base on Matrix architecture which is suitable for portable multimedia applications. The proposed architecture in this paper achieves 40 GOPS of 16-bit fixed-point additions at 200 MHz clock frequency and 250 mW power dissipation. In addition, 1 M-bit SRAM for data registers and 2,048 2-bit processing elements connected by a flexible switching network are integrated in 3.1 mm² in 90 nm low-power CMOS technology. The energy-efficient Matrix architecture supports 2,048-way parallel operations and the programmable functions required for multimedia SoCs.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.11.1512/_p

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@ARTICLE{e89-c_11_1512,
author={Toru SHIMIZU, Masami NAKAJIMA, Masahiro KAINAGA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture},
year={2006},
volume={E89-C},
number={11},
pages={1512-1518},
abstract={This paper describes the design and evaluation of a massively parallel processor base on Matrix architecture which is suitable for portable multimedia applications. The proposed architecture in this paper achieves 40 GOPS of 16-bit fixed-point additions at 200 MHz clock frequency and 250 mW power dissipation. In addition, 1 M-bit SRAM for data registers and 2,048 2-bit processing elements connected by a flexible switching network are integrated in 3.1 mm² in 90 nm low-power CMOS technology. The energy-efficient Matrix architecture supports 2,048-way parallel operations and the programmable functions required for multimedia SoCs.},
keywords={},
doi={10.1093/ietele/e89-c.11.1512},
ISSN={1745-1353},
month={November},}

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TY - JOUR
TI - Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 1512
EP - 1518
AU - Toru SHIMIZU
AU - Masami NAKAJIMA
AU - Masahiro KAINAGA
PY - 2006
DO - 10.1093/ietele/e89-c.11.1512
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2006
AB - This paper describes the design and evaluation of a massively parallel processor base on Matrix architecture which is suitable for portable multimedia applications. The proposed architecture in this paper achieves 40 GOPS of 16-bit fixed-point additions at 200 MHz clock frequency and 250 mW power dissipation. In addition, 1 M-bit SRAM for data registers and 2,048 2-bit processing elements connected by a flexible switching network are integrated in 3.1 mm² in 90 nm low-power CMOS technology. The energy-efficient Matrix architecture supports 2,048-way parallel operations and the programmable functions required for multimedia SoCs.
ER -