This paper describes state-of-the-art process and device technologies for 3-D ICs and the prospect of its possible applications. 3-dimensional monolithic multilayer structures are expected to be appropriate for high density CMOS and image processing devices. Memory cell and fundamental gate structures have been fabricated with stacked PMOS and NMOS layers. A functional model chip which integrates photosensors, A/D converterss and arithmetic logic units demonstrated a real time image processing capability based on the parallel signal processing. The 3-D structure essentially offers a lot of advantages over conventional ULSI structures, but innovative technology improvement in SOI (Silicon-on-Insulator) and refractive metal interconnection is necessary for realizing practically available 3-D chips.

The electrical properties of thin-film SOI (silicon-on-insulator) MOSFETs, revealed by two-dimensional device simulation and experiments using electron-beam recrystallized SOI films, are reviewed and their technological perspectives are discussed. It is shown that thin-film SOI devices have a number of advantages along with some disadvantages. Carrier confinement by an interlayer SiO₂ enhanced the influence of the gate electrode on the channel potential, thereby realized a high punchthrough resistance, making impurity doping into the SOI films unnecessary. The subthreshold slope factor exhibited a nearly ideal behavior, although it was somewhat degraded in the short channel region due to a two-dimensional capacitance coupling between the channel and the source or the drain. A very small capacitive-coupling between the channel and the silicon substrate made the vertical electric field extremely small, bringing about a significant increase in carrier mobility. The kink effect was confirmed to disappear due to an elevated SOI potential, which prevented impact-ionized holes from accumulating in the SOI body. The drain-current overshoot was found to be improved drastically, indicating that excess holes quickly recombine with electrons after gate turn-on, bringing about a stabilized SOI potential. However, the drain breakdown voltage had a tendency to decrease with SOI thinning, which proved to be due to an increase in the electric field at the drain. CMOS ring oscillators made with 2 µm design rule operated approximately three times faster than bulk counterparts at room temperature. It is predicted that thin-film SOI MOSFETs will have a better scalability than bulk MOSFETs not only because of their high punchthrough resistance, but because of a number of additional advantages, such as ease in device isolation as well as shallow junction formation, no impurity-induced problems, and possibility of a different scaling scenario from that in bulk devices, and so on. It is concluded that, despite some technological barries, thin-film SOI MOSFETs can offer quite a viable alternative to bulk MOSFETs as high density ULSIs, while achieving very high speed.

The application of 3D-LSIs for character recognition image sensing processors in described. Three-dimensional LSIs will achieve very high performance by exploiting the structural parallelism by way of the inherence parallelism of an algorithm. As the first step, the three-story structured image sensing processor was implemented integrating 210 pixel photodiodes and 10.4 thousand transistors on a 5.04 mm 11.20 mm die. It is able to sense 6 characters of image at the same time and recognize 64 kind of characters, those are alphabet in capital and lower case, Arabic numerals and some symbols, each consists of 5 7 bit matrix. A four-story structured image sensing processor, which is the second step for realizing the advanced image sensor, integrating 5040 pixel photodiodes and 0.22 million transistors on a 14.3 mm square single die is currently under implementation. The present chip allows 20 times larger degree of data parallelism and several 10 times higher speed of data matching than the previous chip. And some other advantages have been achieved in its functions. Before the implementation of the present chip, its test element circuits were fabricated successively and the functions of the circuit blocks were confirmed. Each floor of 0.6 µm thick SOI film was recrystallized with A_r laser irradiation by the M-shaped beam method with parallel groove structure. The grain boundaries and defects are confined within each ridge region and the defect free single crystal Si film, whose crystal orientation is aligned to the (100) silicon on the lower floor, is grown on each groove region. The maximum temperature of atmosphere during fabrication process was 900. Both chips are made of a number of simple processing elements working in parallel to speed up a computation. So far only several floors can be fabricated as a single die. However the technology has been steadily progressing. The real "intelligent" image sensing processor will be implemented in the near future with 3D integration technology.

A new SOI device structure--a fully DEpleted Lean channel TrAnsistor (DELTA)--which has a new vertical gate structure and an ultra-thin film, bulk Si SOI structure, is proposed. Through experiments and simulation, its fabrication processes and device characteristics are discussed. By using such a new device structure, crystal quality problems caused by recrystallization of poly-Si are solved. DELTA provides a 7.5 times larger channel current than that of conventional planar MOSFETs with the same mask layouts. This is due to a vertical channel structure and a thin film effect. Also, DELTA shows an excellent subthreshold swing of 62 mV/decade. Furthermore, by using a two-carrier device simulator, the punchthrough phenomena in thin film SOI MOSFETs are reexamined from the viewpoint of hole behavior in the substrate. As a result, it was found that the punchthrough resistance of thin film SOI MOSFETs is not always stronger than that of conventional ones. Despite disappearance of the so-called substrate floating effects, attention will still have to be paid to hole behavior in realizing sophisticated SOI devices.

An analytical basis in given for the direct-sum representation circuit equations that played a central role in a previous paper, where the wave transmission between the truncated-guide and the through-guide of a H-plane symmetrical T-junction was shown to be remarkably improved by instaling a fin about one-half height of the guide width on the wall facing the junction plane. The analytical theory yields simple formulas for some circuit-matrix elements. Furthermore, in the application to the fin it is found that only the top of the fin makes a decisive role for the improvement.

We propose and analyze a new type of intersectional optical switch using positive refractive index variation in quantum well structure. The switch structure has a built-in refractive index difference in the waveguide, due to which the incident light is reflected to cross port at the OFF state. When the electric field applied to the electrode (ON state), the built-in refractive index difference vanishes by the positive refractive index variation in the quantum well, and the light transmits to straight port. Low insertion loss of lesser than 1 dB and high extinction ratio of more than 20 dB can be obtained at both cross and straight port.

Cylindrical dielectric waveguide with a periodically varying radius are investigated numerically. The mode-matching method that matches the boundary conditions in the sense of least squares in applied to this problem, using the hybrid-modal representation. The accurate numerical results of the dispersion relations and field distribution are presented for the HE₁₁ mode. It is shown that the attenuation rate in the stopband is significantly smaller than that of TE₀₁ mode, whereas the HE₁₁ mode suffers an additional power leakage due to the coupling with EH₁₁ and HE₁₂ modes of radiation region.