A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs

Tsuneo INABA; Daisaburo TAKASHIMA; Yukihito OOWAKI; Tohru OZAKI; Shigeyoshi WATANABE; Takashi OHSAWA; Kazunori OHUCHI; Hiroyuki TANGO

A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs

Tsuneo INABA, Daisaburo TAKASHIMA, Yukihito OOWAKI, Tohru OZAKI, Shigeyoshi WATANABE, Takashi OHSAWA, Kazunori OHUCHI, Hiroyuki TANGO

Full Text Views

0

Share
Cite this

Summary :

This paper proposes a small 1/4Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F² size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.12 pp.1699-1706

Publication Date: 1996/12/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies)

Category

Cite this

Copy

Tsuneo INABA, Daisaburo TAKASHIMA, Yukihito OOWAKI, Tohru OZAKI, Shigeyoshi WATANABE, Takashi OHSAWA, Kazunori OHUCHI, Hiroyuki TANGO, "A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 12, pp. 1699-1706, December 1996, doi: .
Abstract: This paper proposes a small 1/4Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F² size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e79-c_12_1699/_p

Copy

@ARTICLE{e79-c_12_1699,
author={Tsuneo INABA, Daisaburo TAKASHIMA, Yukihito OOWAKI, Tohru OZAKI, Shigeyoshi WATANABE, Takashi OHSAWA, Kazunori OHUCHI, Hiroyuki TANGO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs},
year={1996},
volume={E79-C},
number={12},
pages={1699-1706},
abstract={This paper proposes a small 1/4Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F² size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.},
keywords={},
doi={},
ISSN={},
month={December},}

Copy

TY - JOUR
TI - A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1699
EP - 1706
AU - Tsuneo INABA
AU - Daisaburo TAKASHIMA
AU - Yukihito OOWAKI
AU - Tohru OZAKI
AU - Shigeyoshi WATANABE
AU - Takashi OHSAWA
AU - Kazunori OHUCHI
AU - Hiroyuki TANGO
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1996
AB - This paper proposes a small 1/4Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F² size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.
ER -