A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU

Katsumi DOSAKA; Akira YAMAZAKI; Naoya WATANABE; Hideaki ABE; Jun OHTANI; Toshiyuki OGAWA; Kazunori ISHIHARA; Masaki KUMANOYA

A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU

Katsumi DOSAKA, Akira YAMAZAKI, Naoya WATANABE, Hideaki ABE, Jun OHTANI, Toshiyuki OGAWA, Kazunori ISHIHARA, Masaki KUMANOYA

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This paper describes a system integrated memory with direct interface to CPU which integrates an SRAM, a DRAM, and control circuitry, including a tag memory (TAG). This memory realizes a computer system without glue chips, and thus enables a computer system which is low cost, low power, and compact size, but still with sufficient performance. And fast clock cycle time and access time is realized using a newly proposed clock driver and internal signal generator. This memory is fabricated with a quad-polysilicon double-metal 0.55-µm CMOS process which is the same as used in a conventional 16-Mb DRAM. The chip size of 145.3mm² is only a 12% increase over the conventional 16-Mb DRAM. The maximum operating frequency is 90-MHz and the operating current at cache-hit is 156-mA. This memory is suitable for various types of computer systems such as personal digital assistants(PDA's), personal computer systems, and embedded controller applications.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.7 pp.948-956

Publication Date: 1996/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))

Category: Memory

Authors

Katsumi DOSAKA
Akira YAMAZAKI
Naoya WATANABE
Hideaki ABE
Jun OHTANI
Toshiyuki OGAWA
Kazunori ISHIHARA
Masaki KUMANOYA

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Katsumi DOSAKA, Akira YAMAZAKI, Naoya WATANABE, Hideaki ABE, Jun OHTANI, Toshiyuki OGAWA, Kazunori ISHIHARA, Masaki KUMANOYA, "A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 7, pp. 948-956, July 1996, doi: .
Abstract: This paper describes a system integrated memory with direct interface to CPU which integrates an SRAM, a DRAM, and control circuitry, including a tag memory (TAG). This memory realizes a computer system without glue chips, and thus enables a computer system which is low cost, low power, and compact size, but still with sufficient performance. And fast clock cycle time and access time is realized using a newly proposed clock driver and internal signal generator. This memory is fabricated with a quad-polysilicon double-metal 0.55-µm CMOS process which is the same as used in a conventional 16-Mb DRAM. The chip size of 145.3mm² is only a 12% increase over the conventional 16-Mb DRAM. The maximum operating frequency is 90-MHz and the operating current at cache-hit is 156-mA. This memory is suitable for various types of computer systems such as personal digital assistants(PDA's), personal computer systems, and embedded controller applications.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e79-c_7_948/_p

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@ARTICLE{e79-c_7_948,
author={Katsumi DOSAKA, Akira YAMAZAKI, Naoya WATANABE, Hideaki ABE, Jun OHTANI, Toshiyuki OGAWA, Kazunori ISHIHARA, Masaki KUMANOYA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU},
year={1996},
volume={E79-C},
number={7},
pages={948-956},
abstract={This paper describes a system integrated memory with direct interface to CPU which integrates an SRAM, a DRAM, and control circuitry, including a tag memory (TAG). This memory realizes a computer system without glue chips, and thus enables a computer system which is low cost, low power, and compact size, but still with sufficient performance. And fast clock cycle time and access time is realized using a newly proposed clock driver and internal signal generator. This memory is fabricated with a quad-polysilicon double-metal 0.55-µm CMOS process which is the same as used in a conventional 16-Mb DRAM. The chip size of 145.3mm² is only a 12% increase over the conventional 16-Mb DRAM. The maximum operating frequency is 90-MHz and the operating current at cache-hit is 156-mA. This memory is suitable for various types of computer systems such as personal digital assistants(PDA's), personal computer systems, and embedded controller applications.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU
T2 - IEICE TRANSACTIONS on Electronics
SP - 948
EP - 956
AU - Katsumi DOSAKA
AU - Akira YAMAZAKI
AU - Naoya WATANABE
AU - Hideaki ABE
AU - Jun OHTANI
AU - Toshiyuki OGAWA
AU - Kazunori ISHIHARA
AU - Masaki KUMANOYA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1996
AB - This paper describes a system integrated memory with direct interface to CPU which integrates an SRAM, a DRAM, and control circuitry, including a tag memory (TAG). This memory realizes a computer system without glue chips, and thus enables a computer system which is low cost, low power, and compact size, but still with sufficient performance. And fast clock cycle time and access time is realized using a newly proposed clock driver and internal signal generator. This memory is fabricated with a quad-polysilicon double-metal 0.55-µm CMOS process which is the same as used in a conventional 16-Mb DRAM. The chip size of 145.3mm² is only a 12% increase over the conventional 16-Mb DRAM. The maximum operating frequency is 90-MHz and the operating current at cache-hit is 156-mA. This memory is suitable for various types of computer systems such as personal digital assistants(PDA's), personal computer systems, and embedded controller applications.
ER -