A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor

Shuping ZHANG; Jinjia ZHOU; Dajiang ZHOU; Shinji KIMURA; Satoshi GOTO

doi:10.1587/transele.E100.C.223

A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor

Shuping ZHANG, Jinjia ZHOU, Dajiang ZHOU, Shinji KIMURA, Satoshi GOTO

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In this paper, a hamburger architecture with a 3D stacked reconfigurable memory is proposed for a 4K motion estimation (ME) processor. By positioning the memory dies on both the top and bottom sides of the processor die, the proposed hamburger architecture can reduce the usage of the signal through-silicon via (TSV), and balance the power delivery network and the clock tree of the entire system. It results in 1/3 reduction of the usage of signal TSVs. Moreover, a stacked reconfigurable memory architecture is proposed to reduce the fabrication complexity and further reduce the number of signal TSVs by more than 1/2. The reduction of signal TSVs in the entire design is 71.24%. Finally, we address unique issues that occur in electronic design automation (EDA) tools during 3D large-scale integration (LSI) designs. As a result, a 4K ME processor with 7-die stacking 3D system-on-chip design is implemented. The proposed design can support real time 3840 × 2160 @ 120 fps encoding at 130 MHz with less than 540 mW.

Publication: IEICE TRANSACTIONS on Electronics Vol.E100-C No.3 pp.223-231

Publication Date: 2017/03/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E100.C.223

Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips)

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Authors

Shuping ZHANG
  Waseda University
Jinjia ZHOU
  Waseda University
Dajiang ZHOU
  Waseda University
Shinji KIMURA
  Waseda University
Satoshi GOTO
  Waseda University

Keyword

3D IC design, motion estimation processor, hamburger architecture, memory stacking

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Shuping ZHANG, Jinjia ZHOU, Dajiang ZHOU, Shinji KIMURA, Satoshi GOTO, "A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor" in IEICE TRANSACTIONS on Electronics, vol. E100-C, no. 3, pp. 223-231, March 2017, doi: 10.1587/transele.E100.C.223.
Abstract: In this paper, a hamburger architecture with a 3D stacked reconfigurable memory is proposed for a 4K motion estimation (ME) processor. By positioning the memory dies on both the top and bottom sides of the processor die, the proposed hamburger architecture can reduce the usage of the signal through-silicon via (TSV), and balance the power delivery network and the clock tree of the entire system. It results in 1/3 reduction of the usage of signal TSVs. Moreover, a stacked reconfigurable memory architecture is proposed to reduce the fabrication complexity and further reduce the number of signal TSVs by more than 1/2. The reduction of signal TSVs in the entire design is 71.24%. Finally, we address unique issues that occur in electronic design automation (EDA) tools during 3D large-scale integration (LSI) designs. As a result, a 4K ME processor with 7-die stacking 3D system-on-chip design is implemented. The proposed design can support real time 3840 × 2160 @ 120 fps encoding at 130 MHz with less than 540 mW.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.223/_p

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@ARTICLE{e100-c_3_223,
author={Shuping ZHANG, Jinjia ZHOU, Dajiang ZHOU, Shinji KIMURA, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor},
year={2017},
volume={E100-C},
number={3},
pages={223-231},
abstract={In this paper, a hamburger architecture with a 3D stacked reconfigurable memory is proposed for a 4K motion estimation (ME) processor. By positioning the memory dies on both the top and bottom sides of the processor die, the proposed hamburger architecture can reduce the usage of the signal through-silicon via (TSV), and balance the power delivery network and the clock tree of the entire system. It results in 1/3 reduction of the usage of signal TSVs. Moreover, a stacked reconfigurable memory architecture is proposed to reduce the fabrication complexity and further reduce the number of signal TSVs by more than 1/2. The reduction of signal TSVs in the entire design is 71.24%. Finally, we address unique issues that occur in electronic design automation (EDA) tools during 3D large-scale integration (LSI) designs. As a result, a 4K ME processor with 7-die stacking 3D system-on-chip design is implemented. The proposed design can support real time 3840 × 2160 @ 120 fps encoding at 130 MHz with less than 540 mW.},
keywords={},
doi={10.1587/transele.E100.C.223},
ISSN={1745-1353},
month={March},}

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TY - JOUR
TI - A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 223
EP - 231
AU - Shuping ZHANG
AU - Jinjia ZHOU
AU - Dajiang ZHOU
AU - Shinji KIMURA
AU - Satoshi GOTO
PY - 2017
DO - 10.1587/transele.E100.C.223
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2017
AB - In this paper, a hamburger architecture with a 3D stacked reconfigurable memory is proposed for a 4K motion estimation (ME) processor. By positioning the memory dies on both the top and bottom sides of the processor die, the proposed hamburger architecture can reduce the usage of the signal through-silicon via (TSV), and balance the power delivery network and the clock tree of the entire system. It results in 1/3 reduction of the usage of signal TSVs. Moreover, a stacked reconfigurable memory architecture is proposed to reduce the fabrication complexity and further reduce the number of signal TSVs by more than 1/2. The reduction of signal TSVs in the entire design is 71.24%. Finally, we address unique issues that occur in electronic design automation (EDA) tools during 3D large-scale integration (LSI) designs. As a result, a 4K ME processor with 7-die stacking 3D system-on-chip design is implemented. The proposed design can support real time 3840 × 2160 @ 120 fps encoding at 130 MHz with less than 540 mW.
ER -