A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits

Tohru KANEKO; Koji HIROSE; Akira MATSUZAWA

doi:10.1587/transele.E101.C.224

A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits

Tohru KANEKO, Koji HIROSE, Akira MATSUZAWA

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A current mirror circuit is often used in Gm-cells and current amplifiers in order to obtain high linearity and high accurate current gain. However, it is expected that a threshold voltage mismatch between transistors pair in the current mirror affects these performances in recent scaled technologies. In this paper, negative effects caused by the mismatch in the current mirror are considered and a new calibration technique for the mismatch issues is proposed. In the current mirror without the mismatch, the high-linearity operation is provided by distortion canceling under the condition that the transistors have the same operating points. The threshold voltage mismatch disturbs the cancellation, therefore the distortion is appeared. In order to address the issue, a new calibration technique using a backgating effect is considered. This calibration can reduce the threshold voltage mismatch directly by controlling the body bias voltage with DACs. According to simulation results with Monte Carlo sampling in 65nm CMOS process, owing to the proposed calibration, the worst HD2 and HD3 are improved by 18.4dB and 11.6dB, respectively. In addition, the standard deviation of the current gain is reduced from 399mdB to 34mdB.

Publication: IEICE TRANSACTIONS on Electronics Vol.E101-C No.4 pp.224-232

Publication Date: 2018/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E101.C.224

Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)

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Authors

Tohru KANEKO
  Tokyo Institute of Technology
Koji HIROSE
  Tokyo Institute of Technology
Akira MATSUZAWA
  Tokyo Institute of Technology

Keyword

current mirror, CMOS, calibration, body bias control

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Tohru KANEKO, Koji HIROSE, Akira MATSUZAWA, "A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits" in IEICE TRANSACTIONS on Electronics, vol. E101-C, no. 4, pp. 224-232, April 2018, doi: 10.1587/transele.E101.C.224.
Abstract: A current mirror circuit is often used in Gm-cells and current amplifiers in order to obtain high linearity and high accurate current gain. However, it is expected that a threshold voltage mismatch between transistors pair in the current mirror affects these performances in recent scaled technologies. In this paper, negative effects caused by the mismatch in the current mirror are considered and a new calibration technique for the mismatch issues is proposed. In the current mirror without the mismatch, the high-linearity operation is provided by distortion canceling under the condition that the transistors have the same operating points. The threshold voltage mismatch disturbs the cancellation, therefore the distortion is appeared. In order to address the issue, a new calibration technique using a backgating effect is considered. This calibration can reduce the threshold voltage mismatch directly by controlling the body bias voltage with DACs. According to simulation results with Monte Carlo sampling in 65nm CMOS process, owing to the proposed calibration, the worst HD2 and HD3 are improved by 18.4dB and 11.6dB, respectively. In addition, the standard deviation of the current gain is reduced from 399mdB to 34mdB.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E101.C.224/_p

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@ARTICLE{e101-c_4_224,
author={Tohru KANEKO, Koji HIROSE, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits},
year={2018},
volume={E101-C},
number={4},
pages={224-232},
abstract={A current mirror circuit is often used in Gm-cells and current amplifiers in order to obtain high linearity and high accurate current gain. However, it is expected that a threshold voltage mismatch between transistors pair in the current mirror affects these performances in recent scaled technologies. In this paper, negative effects caused by the mismatch in the current mirror are considered and a new calibration technique for the mismatch issues is proposed. In the current mirror without the mismatch, the high-linearity operation is provided by distortion canceling under the condition that the transistors have the same operating points. The threshold voltage mismatch disturbs the cancellation, therefore the distortion is appeared. In order to address the issue, a new calibration technique using a backgating effect is considered. This calibration can reduce the threshold voltage mismatch directly by controlling the body bias voltage with DACs. According to simulation results with Monte Carlo sampling in 65nm CMOS process, owing to the proposed calibration, the worst HD2 and HD3 are improved by 18.4dB and 11.6dB, respectively. In addition, the standard deviation of the current gain is reduced from 399mdB to 34mdB.},
keywords={},
doi={10.1587/transele.E101.C.224},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 224
EP - 232
AU - Tohru KANEKO
AU - Koji HIROSE
AU - Akira MATSUZAWA
PY - 2018
DO - 10.1587/transele.E101.C.224
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E101-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2018
AB - A current mirror circuit is often used in Gm-cells and current amplifiers in order to obtain high linearity and high accurate current gain. However, it is expected that a threshold voltage mismatch between transistors pair in the current mirror affects these performances in recent scaled technologies. In this paper, negative effects caused by the mismatch in the current mirror are considered and a new calibration technique for the mismatch issues is proposed. In the current mirror without the mismatch, the high-linearity operation is provided by distortion canceling under the condition that the transistors have the same operating points. The threshold voltage mismatch disturbs the cancellation, therefore the distortion is appeared. In order to address the issue, a new calibration technique using a backgating effect is considered. This calibration can reduce the threshold voltage mismatch directly by controlling the body bias voltage with DACs. According to simulation results with Monte Carlo sampling in 65nm CMOS process, owing to the proposed calibration, the worst HD2 and HD3 are improved by 18.4dB and 11.6dB, respectively. In addition, the standard deviation of the current gain is reduced from 399mdB to 34mdB.
ER -