Negative feedback technique employing high DC gain operational amplifier (op-amp) is one of the most important techniques in analog circuit design. However, high DC gain op-amp is difficult to realize in scaled technology due to a decrease of intrinsic gain. In this paper, high DC gain op-amp using common-gate topology with high power efficiency is proposed. To achieve high DC gain, large output impedance is required but input transistors' drain conductance decreases output impedance of conventional topology such as folded cascode topology with complementary input. This is because bias current of the output side transistors is not separated from the bias current of the input transistors. On the other hand, proposed circuit can suppress a degradation of output impedance by inserting common-gate topology between input and output side. This architecture separates bias current of the input transistors from that of the output side, and hence the effect of the drain conductance of input transistors is reduced. As the result, proposed circuit can increase DC gain about 10,dB compared with the folded cascode topology with complementary input in 65,nm CMOS process. Moreover, power consumption can be reduced because input NMOS and PMOS share bias current. According to the simulation results, for the same power consumption, in the proposed circuit gain-bandwidth product (GBW) is improved by approximately 30% and noise is also reduced in comparison to the conventional topology.

A current mirror circuit is often used in Gm-cells and current amplifiers in order to obtain high linearity and high accurate current gain. However, it is expected that a threshold voltage mismatch between transistors pair in the current mirror affects these performances in recent scaled technologies. In this paper, negative effects caused by the mismatch in the current mirror are considered and a new calibration technique for the mismatch issues is proposed. In the current mirror without the mismatch, the high-linearity operation is provided by distortion canceling under the condition that the transistors have the same operating points. The threshold voltage mismatch disturbs the cancellation, therefore the distortion is appeared. In order to address the issue, a new calibration technique using a backgating effect is considered. This calibration can reduce the threshold voltage mismatch directly by controlling the body bias voltage with DACs. According to simulation results with Monte Carlo sampling in 65nm CMOS process, owing to the proposed calibration, the worst HD2 and HD3 are improved by 18.4dB and 11.6dB, respectively. In addition, the standard deviation of the current gain is reduced from 399mdB to 34mdB.

60GHz wireless communication requires analog baseband circuits having a bandwidth of about 1GHz. This paper presents a wide bandwidth current-mode low pass filter technique which involves current amplifiers, resistors and capacitors. The proposed current-mode filter is obtained by replacing an integrator employing an op-amp with another integrator employing a current amplifier. With the low input impedance current amplifier having little variation of the input impedance, the proposed filter is expected to improve linearity and power efficiency. The proposed current amplifier which employs super source follower topology with complementary input is suitable for the filter because of its class AB operation. Although simulation results shows the conventional current amplifier which employs super source follower topology without the complementary input has 12Ω variation and 30Ω input impedance, the proposed current amplifier has 1Ω variation and 21Ω input impedance. A fourth order 1GHz bandwidth filter which involves the proposed current amplifiers is designed in a 65nm CMOS technology. The filter can achieve IIP3 of 1.3dBV and noise of 0.6mVrms with power consumption of 13mW under supply voltage of 1.2V according to simulation results with layout parasitic extraction models. Active area of the filter is 380μm×170μm.

A continuous-time (CT) ΔΣ analog-to-digital converter (ADC) is a high resolution, wide-bandwidth ADC. A Gm-C filter is suitable for low power consumption and its frequency characteristics for a loop filter of the ADC. However, in practice, distortion generated in the Gm-C filter degrades the SNDR of the ADC, therefore a high-linearity Gm-cell with low power consumption is needed. A flipped voltage follower (FVF) Gm-cell is also used as a high-linearity Gm-cell, but distortion is caused by variation of drain-source voltage of its input transistors. In this paper, a new high-linearity Gm-cell is proposed for the CT ΔΣ ADC in order to address this problem. A proposed topology is a combination of a FVF and a cascode topology. The inserted transistors in the proposed Gm-cell behave as cascode transistors, therefore the drain-source voltage variation of the input transistor and a PMOS transistor for current source which causes distortion is suppressed. Simulation results show the proposed Gm-cell can realize the same linearity as the conventional Gm-cell with reducing 36% power consumption. A 20MHz-bandwidth CT ΔΣ ADC employing the proposed Gm-cells achieves SNDR of 72.4dB with power consumption of 6.8mW. Active area and FoM of the ADC are, respectively, 250μm × 220μm and 50fJ/conv.-step in 65nm CMOS process.